VIRTEX v Spartan 3

[chuk]

Out of interest, would anyone happen to know what is the difference in
performance between a Virtex fpga (not vitex 2) and its equivalent
Spartan3???

Thanks
C

 

[Austin Lesea]

C,

Not enough information, so I will answer a lot of what you did not ask.

Virtex is 6 years old, 0.22 micron technology, Core Vccint = 2.5 volts.
You can look up its speed and capabilities on the website to see how
it performs. Just as a measure, designs can run at 150 MHz with some
care. A real workhorse, and still being used, but seldom do we hear
about it being designed into new equipment. The Mars rovers use 6
V1000's each, for example, to keep the wheels turning, as well as other
supervisory tasks. It has 5V compatibility, hot swap bus without any
power sequencing, and some other really nice features that still make it
a chip of choice. Works at PCI-66 MHz. Has the first Digital Locked
Loops(DLL), dual port BRAM.

http://www.xilinx.com/prs_rls/design_win/0412_marsrover.htm

Virtex E is about 5 years old, 0.18/0.15u hybrid, core Vccint=1.8 volts.
Designs can run at 200 MHz with some care. Virtex E is still being
designed in, but has virtually replaced all Virtex designs (as it is pin
compatible and lower cost), but is now less of a designers choice with
Virtex II and Virtex II Pro being the more common choice. Like Virtex,
it is also 5V tolerant, and hot swap bus friendly. Also a PCI-66 MHz
choice. More DLL's. More BRAM.

Virtex II is about 3 years old, 0.15u, core Vccint=1.5 volts. Designs
can run at 350 MHz with some care, with some designs running a bit
faster in the fastest speedgrade. Virtex II is being designed into many
new boards. VII requires a resistor for 5V tolerance, and also requires
that Vcco be biased on to be hot swap bus friendly. First PCI-X 133 MHz
FPGA. First appearance of the Digital CLock Manager, with both a DLL,
and a frequency synthesizer (DFS). More BRAM.

Virtex II Pro is the lead family, at 0.13u, and also with a Vccint of
1.5 volts. As VII Pro is a better price/performance/capability choice,
with designs at 420 MHz with some care, it is definitely the hands down
winner right now, with an amazing number of new design-ins every month.
Added IBM 405 PowerPC's (tm), and multi-gigabit 3.125 Gbs transceivers.
More BRAM. Faster IO.

http://www.xilinx.com/prs_rls/silicon_vir/0411v2_recrev.htm

Virtex II Pro-X exchanges the 3.125 Gbs transceiver for 10 Gbs
transceivers. An industry first.

http://www.xilinx.com/prs_rls/end_markets/0472atca10g.htm

Virtex 4 has been announced as being the next family, at 90 nm,
Vccint=1.2 volts, and a performance of about 500 MHz (and more), and
general IOs capable of 1 Gbs. See the press announcements for all of
the features that are new.

http://www.xilinx.com/prs_rls/silicon_vir/0465v4arch.htm

Spartan 3 is about a year old, 90 nm with a Vccint=1.2 volts, and was a
redesign of Virtex II for cost. It offers similar performance to a slow
speed grade Virtex II, but with fewer IO standards, and some other
things removed to reduce the die area and cost. It has DCMs, and 18X18
multipliers. It is commonly used to replace ASICs up to very large
volumes (see our press release on sold to date figures).

http://www.xilinx.com/prs_rls/silicon_spart/0471spartanleadership.htm

So, if I take you literally, the original Virtex part is probably half
the speed of a Spartan 3, and since the Virtex part did not have 18X18
multipliers, or DCM's, a Spartan 3 would be a much more powerful chip,
as well as being far less expensive.

The original Virtex is also available as Spartan 2, as is the Virtex E
line as Spartan 2E (smaller gate count parts).

6 products, in 6 years! It will be my 6 year anniversary here at Xilinx
at the end of this month, and I have had the privilege to be involved in
all of the above products.

Austin

chuk wrote:

Out of interest, would anyone happen to know what is the difference in
performance between a Virtex fpga (not vitex 2) and its equivalent
Spartan3???

Thanks
C

 

[Ray Andraka]

Depends. Speed grade, critical paths in design both play into it.
Roughly speaking the 3S-5 is around the same speed as a VirtexE-6, for ~16
bit arithmetic. Faster for random logic without carry chains.
Regardless, it is not a linear relationship. Spartan3 has a different
architecture and the speeds of different elements changed by different
amounts.

chuk wrote:

Out of interest, would anyone happen to know what is the difference in
performance between a Virtex fpga (not vitex 2) and its equivalent
Spartan3???

Thanks
C

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Symon]

I'm looking forward to comments from the CAF regulars on that statement,
Austin! Are we talking 'marketing' years or 'you can buy them' years? Is it
true that in China your age counts from conception? Maybe Spartan 3 is
following that rule? The extra 9 months to sort out the will we/won't we
low-k thing.
With tongue in cheek, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:cb9p4v$cmu2@cliff.xsj.xilinx.com...

Spartan 3 is about a year old,

 

[Austin Lesea]

Symon,

Very funny.

So we are unbelievably successful with S3. Is that our fault that we
somehow did not figure that they would be instantly shipped once they
got packaged?

Triple whammy: 1) great part 2) great price 3)dot.com ending.

Did you bother to read the S3 press release? 500K S3's in 2003?

That is one helluva lot of FPGAs.....

Some would have you beleive that 90nm was "too risky" and "had
availability issues" .... that is until they have their 90nm offering!

Never even considered lo-K for S3 (too much $$$ for too little benefit).

Lo-K was a Virtex II Pro 'issue' that we had to correct by process
tweaks and design. Let's face it, if we can still meet all of the
specifications without lo-K, why bother with the cost and reliability
issues?

Austin



Symon wrote:

I'm looking forward to comments from the CAF regulars on that statement,
Austin! Are we talking 'marketing' years or 'you can buy them' years? Is it
true that in China your age counts from conception? Maybe Spartan 3 is
following that rule? The extra 9 months to sort out the will we/won't we
low-k thing.
With tongue in cheek, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:cb9p4v$cmu2@cliff.xsj.xilinx.com...

Spartan 3 is about a year old,

 

[Ray Andraka]

Provided you don't use the carry chain.

Austin Lesea wrote:

C,

Virtex II is about 3 years old, 0.15u, core Vccint=1.5 volts. Designs
can run at 350 MHz with some care, with some designs running a bit
faster in the fastest speedgrade. Virtex II is being designed into many

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Jim Granville]

Austin Lesea wrote:

Symon,

Very funny.

So we are unbelievably successful with S3. Is that our fault that we
somehow did not figure that they would be instantly shipped once they
got packaged?

Triple whammy: 1) great part 2) great price 3)dot.com ending.

er ? In this part of the world, (and many others) dot.com == dot.bomb
- is that what you meant to convey ?

Did you bother to read the S3 press release? 500K S3's in 2003?

That is one helluva lot of FPGAs.....

The other press release says $750M in Spartans (all suffixes) and 80M
pcs. ( ASP of just over $9)
So that makes your 'helluva lot' just 0.625% of the total shipped,
and Xilinx gives excuses for not being able to meet demand ?.
It is OK to 'chest beat' about "your new asic", but if Xilinx cannot
attain ASIC volumes, you will have to work hard to get those
design wins.
-jg

 

[Austin Lesea]

Jim,

See below,

Austin

Jim Granville wrote:

Austin Lesea wrote:

Symon,

Very funny.

So we are unbelievably successful with S3. Is that our fault that we
somehow did not figure that they would be instantly shipped once they
got packaged?

Triple whammy: 1) great part 2) great price 3)dot.com ending.


er ? In this part of the world, (and many others) dot.com == dot.bomb
- is that what you meant to convey ?

Yes.

Did you bother to read the S3 press release? 500K S3's in 2003?

That is one helluva lot of FPGAs.....


The other press release says $750M in Spartans (all suffixes) and 80M
pcs. ( ASP of just over $9)
So that makes your 'helluva lot' just 0.625% of the total shipped,
and Xilinx gives excuses for not being able to meet demand ?.
It is OK to 'chest beat' about "your new asic", but if Xilinx cannot
attain ASIC volumes, you will have to work hard to get those
design wins.
-jg

I see the glass as half full, you see it as totally empty. All a matter
of perspective.

One could say that any recently introduced product is a 'failure'
because it does not even register on the combined income of the last
three products.

No excuses offered, merely an explanation.

 

[Jim Granville]

Austin Lesea wrote:

Jim,

snip
Did you bother to read the S3 press release? 500K S3's in 2003?

That is one helluva lot of FPGAs.....



The other press release says $750M in Spartans (all suffixes) and 80M
pcs. ( ASP of just over $9)
So that makes your 'helluva lot' just 0.625% of the total shipped,
and Xilinx gives excuses for not being able to meet demand ?.
It is OK to 'chest beat' about "your new asic", but if Xilinx cannot
attain ASIC volumes, you will have to work hard to get those
design wins.
-jg


I see the glass as half full, you see it as totally empty. All a matter
of perspective.

One could say that any recently introduced product is a 'failure'
because it does not even register on the combined income of the last
three products.

No excuses offered, merely an explanation.

You may have missed the point a little.
* Symon commented on the general availability of S3 devices.
* You explained that customer demand exceeded Xilinx's ability to supply.
* I looked at the WEB references you gave, and they indeed confirm that
actual volumes of the S3 are not great, for 2003.

All three can be true, and I am not sure where 'totally empty' and
'failure' come from; your words, not mine.

Of course they are new, and yes they are ramping, but the stats
indicate a 2003 run rate of maybe 20M pcs/yr in Spartan ( educated guess
from 80M over 6 yrs).
With S3 numbers being appx 1/40 of Spartan shipments, that would seem
to be very early in the ramp - which confirms Symon's observation.

Could you give us 1H 2004 volumes, and present lead times, for S3
devices ?
As a designer, a valid question is: Has Xilinx 'caught up' enough, so
that a design could use these devices, and not have a supply problem ?

-jg

 

[Uwe Bonnes]

Jim Granville <no.spam@designtools.co.nz> wrote:
....
: Could you give us 1H 2004 volumes, and present lead times, for S3
: devices ?
: As a designer, a valid question is: Has Xilinx 'caught up' enough, so
: that a design could use these devices, and not have a supply problem ?

If at least distributors could offer (paid) engineering samples, not only
long lead times...
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Austin Lesea]

Jim,


-snip-

Could you give us 1H 2004 volumes, and present lead times, for S3
devices ?
As a designer, a valid question is: Has Xilinx 'caught up' enough, so
that a design could use these devices, and not have a supply problem ?

-jg

No, I can not do that Jim. To get supply information, you must contact
your distributor. To get how many we have, I have to wait for a press
release (confidential and restricted information can not be released on
this newsgroup)just like you do.

I am told that distributors do have part/package combinations in stock
on the shelf. I am also told that some devices are still in short
supply. We are fab'ing as many wafers as we possibly can to catch up
(projecting ahead), but demand is ramping faster.

To that end, and by your definition, perhaps we have not caught up on
some devices (glass is half empty), but we are doing the best we can and
making a lot of progress (glass is half full).

No one is going to post on this newsgroup that their part was on the
shelf when they ordered it ('dog bites man' is not news). But if the
part is not on the shelf, then we hear all about it in this forum ('man
bites dog' is news).

I advise anyone who is designing (regardless of the part or family) to
work closely with your distributor, (as anyone would who buys in the
quantities that we are seeing for S3).


Austin

PS: I did not intend to put "words in your mouth". Poetic license
#23210098 issued 5/14/53

 

[Symon]

"Austin Lesea" <austin@xilinx.com> wrote in message
news:cbc6gt$cn31@cliff.xsj.xilinx.com...

I advise anyone who is designing (regardless of the part or family) to
work closely with your distributor, (as anyone would who buys in the
quantities that we are seeing for S3).

Very good advice Austin. To be fair to Xilinx, our Distie, knowing our

volumes and lead time requirements, advised us to steer clear of S3 for a
while. From some of the posts I read on here, this appears to have been the
correct thing to do for my company. (Although, as you say Austin, the people
who got their parts don't post here to complain!)
When I try to see things from Xilinx's point of view, of course they're
gonna supply their biggest customers first, and keep pushing the product
with as much hype as possible to these main guys, fair enough. Also, don't
forget that if it weren't for the big guys buying loads of parts, the small
guys wouldn't get any of these parts _ever_. It's just that the marketing
spiel eventually becomes a little frustrating!
Maybe what we need is not only price vs. volume data, but lead-time vs.
volume too!
Finally, you can be sure people are impressed with the product, Austin.
No-one would complain about lead-time if the chips were a pile of poo.
Cheers, Syms.

 

[Finn S. Nielsen]

"Austin Lesea" <austin@xilinx.com> skrev i en meddelelse
news:cb9t2d$cm02@cliff.xsj.xilinx.com...

Symon,

Very funny.

So we are unbelievably successful with S3. Is that our fault that we
somehow did not figure that they would be instantly shipped once they
got packaged?

Triple whammy: 1) great part 2) great price 3)dot.com ending.

Did you bother to read the S3 press release? 500K S3's in 2003?

That is one helluva lot of FPGAs.....

Some would have you beleive that 90nm was "too risky" and "had
availability issues" .... that is until they have their 90nm offering!

Never even considered lo-K for S3 (too much $$$ for too little benefit).

Lo-K was a Virtex II Pro 'issue' that we had to correct by process
tweaks and design. Let's face it, if we can still meet all of the
specifications without lo-K, why bother with the cost and reliability
issues?

Austin

Austinn,

It seems to me that your a beating about the bush about the availability of
spartan-3 chips.

The thing is that Xilinx was very quick to announce the SP3 family very
early, before even thinking
seriously/or knowing about when they could actually be delivered (even in
sample quantity).
Add to that some problems about the design of IO's cells to get them 3.3V
tolerant and I think also
some uncertaintay about what functions should actually finally go into the
chips - caused extra delay
from protoypes to tested sample/volume production. Another thing is that all
the software people
involved in writing ISE and the EDK kits had to keep up to deliver the SW in
time for the release of the chips

It has given Xilinx and SP3 a somewhat bad reputation in the electronics
business and propably
also had the effect that a lot of designs haven't been done with SP3 (I know
of a few at my job).

Guess it's always a balance when to announce a new family. Too early gives a
bad reputation and to late,
causes the loss of design-in's. I'd say in this case it was announced 6
months too early.
Don't know how it's going to go with the virtex-4 family, but I suspect we
have the same story here,
but I hope the delay won't bee as large as for SP3, as the 80 ns process is
more mature and so are
fx. the design of IO blocks with it ;-)

Thanks anyway for designing good FPGA's. Keep up the good work !

Finn Nielsen
Denmark

 

[Austin Lesea]

Finn,

I take issue with the unsupported spin by competitors accusing us of
introducing a product "too early."

First of all, very few products get introduced totally problem free.
Yes, we have had an errata sheet with a new product, but that is a
service, not something to be ashamed of. In fact, compared to others in
this industry, our errata sheet is at least less than a couple of pages,
and most often a single sheet. Others have in excess of 20 or more
known bugs, with many different mask revisions, which is hell to keep
track of. So are we too early when we have a few errata, but we do not
force a customer to live through three mask revisions? That to me is
too early: announcing a product that is too buggy, and isn't ready.
What does it matter that it is "on the shelf?"

Secondly, there has been incredible unexpected business in Spartan 3.
So, did we not have enough supply? Yes. Did we intentionally introduce
it too early so we would make people unhappy? No.

Third, I can say nothing about the software (not my area), so no defense
offered here. I will let them offer one, or an apology, whichever is
appropriate.

Fourth, and lastly, Virtex 4 was announced today being shipped to early
access customers. That means it is real. Now comes the fun part,
making lots more, and sampling them. I will not disagree that the
sampling phase will be a real challenge, but who else has a triple oxide
500 MHz FPGA with IBM Power PC's, 10 Gbs transceivers, FIFO BRAM, 48bit
DSP with MAC...... no one. It isn't called the "bleeding edge" for nothing.

But if you are not there (on the edge of the technology juggernaut), you
are nowhere.


Austin

 

[rickman]

Austin Lesea wrote:

I am told that distributors do have part/package combinations in stock
on the shelf. I am also told that some devices are still in short
supply. We are fab'ing as many wafers as we possibly can to catch up
(projecting ahead), but demand is ramping faster.

I asked for an update on the XC3S400-4FG456C and was told 12 weeks
(that's three months, right?) or "open order entry" for the ES version.
They did not say they had had even the ES parts on the shelf. Can you
give me a heads up on who might have stock on this part?

Also, what exactly is the difference between the production and ES parts
at this point? I believe the 3S400 parts are claimed to be in
"production" for many months now. Where do the ES parts come from at
this late stage?

PS: I did not intend to put "words in your mouth". Poetic license
#23210098 issued 5/14/53

When replying to my posts, please keep your poetic license in your
pocket. This is prose, not poetry.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Austin Lesea]

Rick,

---snip----

I asked for an update on the XC3S400-4FG456C and was told 12 weeks
(that's three months, right?) or "open order entry" for the ES version.
They did not say they had had even the ES parts on the shelf. Can you
give me a heads up on who might have stock on this part?

Sorry, I suspect that S3 ES parts are available only through Xilinx,
which means that we have stock, and are awaiting a disti order. Only
those disti's that want to (we can not force them) will buy ES material,
as they do not want to be "stuck" with ES stock (as then they have to
write it).

Also, what exactly is the difference between the production and ES parts
at this point?

Basically none. After the first masks of the first family members,
errata are fixed, and the second or third masks made are just awaiting
the HTOL (high temperature operating life), ESD, and other reliability
tests before they can be officially called production. Same silicon,
more paper pedigree. Again, contact you disti and FAE for exact details
on any specific part. One good way is to request the errata sheet for
the two parts. If there is no errata sheet for a part, it has no
problems, and that usually means it is the second mask made in the
family, as the first one's errata are fixed (if any).

I believe the 3S400 parts are claimed to be in
"production" for many months now. Where do the ES parts come from at
this late stage?

As soon as we have production, no one wants the ES anymore. Sometimes
we have to write off a lot of ES material as it can not be sold (or
donate it to schools and universities -- see the Xilinx University
Program online! Do not email me for the parts!).

 

[Austin Lesea]

http://www.xilinx.com/products/spartan3/s3boards.htm

is the $99 S3 starter kit (orderable over the web).

Austin

PS: for anyone playing around with ancient FPGAs, give yourself a
break, and just order the latest technology to play with.

 

[Symon]

Austin,
What sort of JTAG download cable is included in that kit? I don't recognise
it.
Ta, Syms.

"Austin Lesea" <austin@xilinx.com> wrote in message
news:cbq4cp$2kr4@cliff.xsj.xilinx.com...

http://www.xilinx.com/products/spartan3/s3boards.htm

is the $99 S3 starter kit (orderable over the web).

Austin

PS: for anyone playing around with ancient FPGAs, give yourself a
break, and just order the latest technology to play with.

 

[Jim Granville]

Austin Lesea wrote:

http://www.xilinx.com/products/spartan3/s3boards.htm

is the $99 S3 starter kit (orderable over the web).

Austin

PS: for anyone playing around with ancient FPGAs, give yourself a
break, and just order the latest technology to play with.

Nice system.
Can you refresh us, as it's not clear on the link above.
IIRC, PicoBlaze is free [Xilinx hosted understood ],
and MicroBlaze is $$ - correct ?
-jg

 

[Austin Lesea]

Symon,

Do not know. I'll find out.

Austin

Symon wrote:

Austin,
What sort of JTAG download cable is included in that kit? I don't recognise
it.
Ta, Syms.

"Austin Lesea" <austin@xilinx.com> wrote in message
news:cbq4cp$2kr4@cliff.xsj.xilinx.com...

http://www.xilinx.com/products/spartan3/s3boards.htm

is the $99 S3 starter kit (orderable over the web).

Austin

PS: for anyone playing around with ancient FPGAs, give yourself a
break, and just order the latest technology to play with.