A
Andreas Weder
Guest
hi
I have some problems with frame address calculation for readback on
Xilinx Virtex II Pro XC2VP7.
This is what I know about FAR:
- have to write 00 to bits 26 and 25 for CLB's
- have to write 01 to bits 26 and 25 for BRAM's
- have to write 10 to bits 26 and 25 for BRAMINT
- I have to shift the CLB or BRAM column to bit 17
- I have to shift the number of the frame inside a block to bit 9
My problem is where to find the CLB column. I thougt I could use the
X-coordinates from floorplanner or fpga-editor. But this is wrong.
Any ideas?
--
Andreas Weder
Hochschulstraße 8
01069 Dresden, Germany
+49 162 / 4099116
andreas@lowtexx.de
I have some problems with frame address calculation for readback on
Xilinx Virtex II Pro XC2VP7.
This is what I know about FAR:
- have to write 00 to bits 26 and 25 for CLB's
- have to write 01 to bits 26 and 25 for BRAM's
- have to write 10 to bits 26 and 25 for BRAMINT
- I have to shift the CLB or BRAM column to bit 17
- I have to shift the number of the frame inside a block to bit 9
My problem is where to find the CLB column. I thougt I could use the
X-coordinates from floorplanner or fpga-editor. But this is wrong.
Any ideas?
--
Andreas Weder
Hochschulstraße 8
01069 Dresden, Germany
+49 162 / 4099116
andreas@lowtexx.de