Virtex II Pro and 3rd party devices in one JTAG chain?

[MM]

Does anyone know if it is OK to have 3rd party devices in one JTAG chain
with Xilinx FPGAs and CPLDs? The Xilinx devices I am using are XC2VP4 and
XC9572XL...


Thanks,
/Mikhail

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To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")

 

[Symon]

Mikhail,
If you mean can you still program the FPGAs over the JTAG then yes, it's OK.
I've done it before with a Virtex II and an Intel StrongArm processor. IIRC
you need a boundary scan discription file for the 3rd party IC to keep
Impact happy. Sorry I can't be more specific, this work was at a previous
company.
Cheers, Syms.
"MM" <mbmsv@yahoo.com> wrote in message
news:c6j4mp$cb5n8$1@ID-204311.news.uni-berlin.de...

Does anyone know if it is OK to have 3rd party devices in one JTAG chain
with Xilinx FPGAs and CPLDs? The Xilinx devices I am using are XC2VP4 and
XC9572XL...


Thanks,
/Mikhail

--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")

 

[MM]

Symon,

Yes, that is what I was asking whether. Thanks. Can you tell what you were
trying to achieve by combining these two beasts in one JTAG chain? I want to
be able to use boundary scan equipment to verify connections between the
chips in the board manufacturing phase. I am still not sure if it is worth
the effort and money considering that I won't get 100% pin coverage... I
would be curious to know how many people are actually using Intellitech and
similar tools for testing their boards? Sorry if this is OT...

Thanks,
/Mikhail

--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")



"Symon" <symon_brewer@hotmail.com> wrote in message
news:c6k0bo$clejr$1@ID-212844.news.uni-berlin.de...

Mikhail,
If you mean can you still program the FPGAs over the JTAG then yes, it's
OK.
I've done it before with a Virtex II and an Intel StrongArm processor.
IIRC
you need a boundary scan discription file for the 3rd party IC to keep
Impact happy. Sorry I can't be more specific, this work was at a previous
company.
Cheers, Syms.

 

[Symon]

Hi Mikhail,
We did exactly as you describe, i.e. we "want[ed] to be able to use boundary
scan equipment to verify connections between the chips in the board
manufacturing phase."! All the parts were BGAs so it was a good way to check
connections. Also we used the JTAG on the processor to program its flash
memory with boot loader code after the boards were populated. Finally, we
used just one chain because it needed a smaller connector than multiple
chains.
As to whether boundary scan's worth it or not, that depends on your volume,
yeild, rework cost for completed units, etc.
Cheers, Syms.
"MM" <mbmsv@yahoo.com> wrote in message
news:c6k2fv$cmssq$1@ID-204311.news.uni-berlin.de...

Symon,

Yes, that is what I was asking whether. Thanks. Can you tell what you were
trying to achieve by combining these two beasts in one JTAG chain? I want
to
be able to use boundary scan equipment to verify connections between the
chips in the board manufacturing phase. I am still not sure if it is worth
the effort and money considering that I won't get 100% pin coverage... I
would be curious to know how many people are actually using Intellitech
and
similar tools for testing their boards? Sorry if this is OT...

Thanks,
/Mikhail

 

[Bob]

We use Corelis tools to verify ball-to-ball connectivity. Every board that
we manufacture utilizes the JTAG chain to test as much of the board that is
possible. Our chains involve Xilinx FPGA's and many other types of JTAG-able
devices.

Bob



"MM" <mbmsv@yahoo.com> wrote in message
news:c6k2fv$cmssq$1@ID-204311.news.uni-berlin.de...

Symon,

Yes, that is what I was asking whether. Thanks. Can you tell what you were
trying to achieve by combining these two beasts in one JTAG chain? I want
to
be able to use boundary scan equipment to verify connections between the
chips in the board manufacturing phase. I am still not sure if it is worth
the effort and money considering that I won't get 100% pin coverage... I
would be curious to know how many people are actually using Intellitech
and
similar tools for testing their boards? Sorry if this is OT...

Thanks,
/Mikhail

--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")



"Symon" <symon_brewer@hotmail.com> wrote in message
news:c6k0bo$clejr$1@ID-212844.news.uni-berlin.de...
Mikhail,
If you mean can you still program the FPGAs over the JTAG then yes, it's
OK.
I've done it before with a Virtex II and an Intel StrongArm processor.
IIRC
you need a boundary scan discription file for the 3rd party IC to keep
Impact happy. Sorry I can't be more specific, this work was at a
previous
company.
Cheers, Syms.