Virtex II LVDS plus DDR?

[Mark]

Howdy Gurus,

I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS
i/o and their DDR i/o, but haven't found a clear explanation yet of
the two being used together.

DDR by itself is pretty obvious, but the LVDS appears to work by a
magical connection between two neighboring IOBs.

For an LVDS input pair (Dp and Dn) coming in at DDR, does the
differential-to-single-ended conversion take place before the input
flops of the IOB?

i.e., if Dp comes into IOB1 and Dn comes into IOB2, is there a
single-ended output from some magical cell after the IOBs that I have
to feed into two general CLB flops to get my registered Qre (rising
edge) and Qfe (falling edge) outputs? (or specify an attribute to
request that they be mapped into IOB flops?)

Or, if the conversion to single-ended is done before the IOB flops,
then the single-ended DDR data is easily clocked into the two IOB
flops on opposite clock edges, right?

If that is the case:
Dp -> IPAD -> IOB1 ---\
(diff2single) >----- Dddr -----> to IOB flops
Dn -> IPAD -> IOB2 ---/ (single-ended)

then which flops (those in IOB1 or IOB2) get the DDR data?

A clear explanation would be great, code/constraint snippets would be
lovely!

Thanks,

MarkJ

 

[John Providenza]

Mark -

The conversion between differential and single-ended happens
very close to the pin, so on the input side, you effectively
see a single ended signal going into the DDR flops. On the
output side, single ended data from the flops goes to the
output buffer (in the IOBs) and is converted into differential.


Here's some code I've used with XST to drive a DDR style
signal out to LVDS pins on a Virtex II-Pro:

output [13:0] dac_even_p; // dac even data port
output [13:0] dac_even_n; // dac even data port

// instantiate the DDR output cell
FDDRRSE u0ddr_q (.C0(clk_dac_n),.C1(clk_dac),
.R(1'b0), .S(1'b0),.CE(1'b1),
.D0(d_pipe[0]), .D1(dac_data[0]),
.Q(dac_even[0])
);

// instantiate the LVDS driver
OBUFDS_LVDS_25 u0obuf_even(.O (dac_even_p[0]), .OB (dac_even_n[0]),
.I (dac_even[0]));

As far as I know, you MUST instantiate DDR output flops, XST can't
infer them. It is able to infer DDR input flops.

You need to be careful that you actually assign CORRECT adjacent
pins for the LVDS signals in the .ucf file! Not all adjacent
pins can be paired up. Also, the polarities are fixed, ie,
one pin is the N, the other is the P and you can't swap them.

I hope this helps!

John P


jjohnson@cs.ucf.edu (Mark) wrote in message news:<c88fa005.0408201343.4a29a701@posting.google.com>...

Howdy Gurus,

I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS
i/o and their DDR i/o, but haven't found a clear explanation yet of
the two being used together.

DDR by itself is pretty obvious, but the LVDS appears to work by a
magical connection between two neighboring IOBs.

For an LVDS input pair (Dp and Dn) coming in at DDR, does the
differential-to-single-ended conversion take place before the input
flops of the IOB?

i.e., if Dp comes into IOB1 and Dn comes into IOB2, is there a
single-ended output from some magical cell after the IOBs that I have
to feed into two general CLB flops to get my registered Qre (rising
edge) and Qfe (falling edge) outputs? (or specify an attribute to
request that they be mapped into IOB flops?)

Or, if the conversion to single-ended is done before the IOB flops,
then the single-ended DDR data is easily clocked into the two IOB
flops on opposite clock edges, right?

If that is the case:
Dp -> IPAD -> IOB1 ---\
(diff2single) >----- Dddr -----> to IOB flops
Dn -> IPAD -> IOB2 ---/ (single-ended)

then which flops (those in IOB1 or IOB2) get the DDR data?

A clear explanation would be great, code/constraint snippets would be
lovely!

Thanks,

MarkJ