Virtex-II DCM frequency synthesizer

[Evgeni]

I'm using Virtex-II DCM frequency synthesizer to get 52MHz clock from
16MHz. Two questions:
1) Since my input frequency is outside the minimum operating range in
the low frequency mode(24MHz), I cannot use CLKFB feedback. Is there
any easy way to override this restriction.
2) I tried doing this freq. conversion without CLKFB using
CLKFX_DIVIDE = 4, CLKFX_MULTIPLY=13 parameters. Output is connected to
CLKFX. Input is connected directly from external source. I'm measuring
64MHz on that output instead of 52MHz. Is there anything wrong with
those particular parameters?

Thanks,
Eugene.

 

[Jay]

"Evgeni" <evgenist@yahoo.com>
??????:82bfabfe.0310281848.3d2812f0@posting.google.com...

I'm using Virtex-II DCM frequency synthesizer to get 52MHz clock from
16MHz. Two questions:
1) Since my input frequency is outside the minimum operating range in
the low frequency mode(24MHz), I cannot use CLKFB feedback. Is there
any easy way to override this restriction.
double your clock outside

2) I tried doing this freq. conversion without CLKFB using
CLKFX_DIVIDE = 4, CLKFX_MULTIPLY=13 parameters. Output is connected to
CLKFX. Input is connected directly from external source. I'm measuring
64MHz on that output instead of 52MHz. Is there anything wrong with
those particular parameters?
it seems your parameters are not recognized by the implementation, and the

default parameters (4/1) are used.
check your constraints.

 

[Peter Alfke]

Why do you want feedback?
Your 16 MHz and 52 MHz clocks have strange phase relationships for 3
periods of the 16 MHz and 12 periods of the 52 MHz, until they meet
again every 250 ns. Is it really important to have this one situation
phase aligned, when all the others inevitably are not?

Peter Alfke
=================================
Jay wrote:

"Evgeni" <evgenist@yahoo.com
??????:82bfabfe.0310281848.3d2812f0@posting.google.com...
I'm using Virtex-II DCM frequency synthesizer to get 52MHz clock from
16MHz. Two questions:
1) Since my input frequency is outside the minimum operating range in
the low frequency mode(24MHz), I cannot use CLKFB feedback. Is there
any easy way to override this restriction.
double your clock outside

2) I tried doing this freq. conversion without CLKFB using
CLKFX_DIVIDE = 4, CLKFX_MULTIPLY=13 parameters. Output is connected to
CLKFX. Input is connected directly from external source. I'm measuring
64MHz on that output instead of 52MHz. Is there anything wrong with
those particular parameters?
it seems your parameters are not recognized by the implementation, and the
default parameters (4/1) are used.
check your constraints.

 

[Austin Lesea]

Evgeni,

No, you can not use CLKFB below 24 MHz.

The M and D value is not appearing to be set at all (default is X4).

Austin

Evgeni wrote:

I'm using Virtex-II DCM frequency synthesizer to get 52MHz clock from
16MHz. Two questions:
1) Since my input frequency is outside the minimum operating range in
the low frequency mode(24MHz), I cannot use CLKFB feedback. Is there
any easy way to override this restriction.
2) I tried doing this freq. conversion without CLKFB using
CLKFX_DIVIDE = 4, CLKFX_MULTIPLY=13 parameters. Output is connected to
CLKFX. Input is connected directly from external source. I'm measuring
64MHz on that output instead of 52MHz. Is there anything wrong with
those particular parameters?

Thanks,
Eugene.

 

[Martin Euredjian]

2) I tried doing this freq. conversion without CLKFB using
CLKFX_DIVIDE = 4, CLKFX_MULTIPLY=13 parameters. Output is connected to
CLKFX. Input is connected directly from external source. I'm measuring
64MHz on that output instead of 52MHz. Is there anything wrong with
those particular parameters?

DCM's can be a bundle of fun if you don't handle their post-reset behavior
properly. You have to check the "LOCKED" pin and, if lock is not achieved,
toggle the "RST" pin.

As an example, on a working design, I hold "RST" high for about 10us and
check "LOCKED" about 200us later. If lock is not achieved the process
repeats. The reset tree going into the rest of the design is held in reset
until the DCM's are healthy. Check the data sheets for lock time
information, it isn't instantaneus.

O yeah, critical in the above is to use a "garbage" clock to time the DCM
reset/monitoring function. Don't make the mistake of using a clock coming
out of a DCM that is being reset or you'll go around in circles for a while.
Who in their right mind would do that, right? :-(


--
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Martin Euredjian

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