Virtex: Foundation 3.1 Error

[Nyoman Yani H]

Dear all <BR>
&amp;nbsp;I am using Xilinx Foundation 3.1i to implement my <BR>
design into XSV board and debug using hardware <BR>
&amp;nbsp;debugger. <BR>
&amp;nbsp;I am trying to instantiate readback symbol in my <BR>
design using this file : <p> library IEEE; <BR>
&amp;nbsp;use IEEE.std_logic_1164.all; <BR>
&amp;nbsp;library virtex; <BR>
&amp;nbsp;use virtex.components.all; <p> entity rdbk is <BR>
&amp;nbsp;port ( <BR>
&amp;nbsp;rt, clk : in STD_LOGIC; <BR>
&amp;nbsp;rd, rip_p : out STD_LOGIC <BR>
&amp;nbsp; <BR>
&amp;nbsp;end rdbk; <p> architecture xilinx of rdbk is <p> begin <p> U0: RDBK port map (TRIG =&gt; rt, DATA =&gt; rd, RIP =&gt; <BR>
&amp;nbsp;rip_p); <BR>
&amp;nbsp;U1: RDCLK port map (I =&gt; clk); <p> end xilinx; <p> But I found these errors at implementation steps : <p> Error L-3/C0 : #0 Error: <BR>
&amp;nbsp;:/Xilinx/active/projects/and3_gat/readback.vhd line <BR>
&amp;nbsp;-3 Library logical name VIRTEX is not mapped to a <BR>
&amp;nbsp;host directory. (VSS-1071) (FPGA-hci-hdlc-unknown) <BR>
&amp;nbsp;&amp;nbsp;Error L4/C0 : #0 Error: <BR>
&amp;nbsp;E:/Xilinx/active/projects/and3_gat/readback.vhd line <BR>
&amp;nbsp;4 No selected element named COMPONENTS is defined <BR>
&amp;nbsp;for this prefix. (VSS-573) <BR>
&amp;nbsp;&amp;nbsp;Error L13/C0 : #0 Error: <BR>
&amp;nbsp;E:/Xilinx/active/projects/and3_gat/readback.vhd line <BR>
&amp;nbsp;13 The intermediate file for entity RDBK is not in <BR>
&amp;nbsp;the library bound to WORK. (VSS-1084) <p> What do they mean ? I really apreciate the feedback <BR>
&amp;nbsp;from all of you. <p> Regards <p> Nyoman Yani