Virtex-E power trace

[Stefan Tillich]

Hello,

We are currently trying to measure the power consumption of a Xilinx
Virtex-E FPGA on a custom-made circuit-board.

The FPGA is configured with a design which performs AES operations.
Power consumption is measured with a sensor resistor between the
FPGA's ground and the board's ground.

The trace shows activity of the AES design very clearly but when there
is no operation performed, then there is almost no transient current
flow.

In our opinion, at least some activity due to the loading of the clock
tree should be visible.

I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
synthesizer generates some kind of power management for the design
(e.g. clock gating) so that there is nearly no power consumption, when
the design is not active? And if it does, is it possible to turn that
optimization behaviour off?

Best regards
Stefan Tillich

 

[Andrew Paule]

how many dB is you circuit capable of?

Maybe Peter (Alfke) will know how much current a minimal clock tree will
take, but I would guess not much - these things are designed for LOW
current operation.

Andrew

Stefan Tillich wrote:

Hello,

We are currently trying to measure the power consumption of a Xilinx
Virtex-E FPGA on a custom-made circuit-board.

The FPGA is configured with a design which performs AES operations.
Power consumption is measured with a sensor resistor between the
FPGA's ground and the board's ground.

The trace shows activity of the AES design very clearly but when there
is no operation performed, then there is almost no transient current
flow.

In our opinion, at least some activity due to the loading of the clock
tree should be visible.

I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
synthesizer generates some kind of power management for the design
(e.g. clock gating) so that there is nearly no power consumption, when
the design is not active? And if it does, is it possible to turn that
optimization behaviour off?

Best regards
Stefan Tillich

 

[Peter Alfke]

I am sure the answer to your first question is: No.
But to convince yourself, just implement a toggling flip-flop, clocked
like everything else, and bring the Q out on a spare pin...
Peter Alfke

Stefan Tillich wrote:

Hello,

We are currently trying to measure the power consumption of a Xilinx
Virtex-E FPGA on a custom-made circuit-board.

The FPGA is configured with a design which performs AES operations.
Power consumption is measured with a sensor resistor between the
FPGA's ground and the board's ground.

The trace shows activity of the AES design very clearly but when there
is no operation performed, then there is almost no transient current
flow.

In our opinion, at least some activity due to the loading of the clock
tree should be visible.

I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
synthesizer generates some kind of power management for the design
(e.g. clock gating) so that there is nearly no power consumption, when
the design is not active? And if it does, is it possible to turn that
optimization behaviour off?

Best regards
Stefan Tillich

 

[Peter Alfke]

I am sure the answer to your first question is: No.
But to convince yourself, just implement a toggling flip-flop, clocked
like everything else, and bring the Q out on a spare pin...
Peter Alfke

Stefan Tillich wrote:

Hello,

We are currently trying to measure the power consumption of a Xilinx
Virtex-E FPGA on a custom-made circuit-board.

The FPGA is configured with a design which performs AES operations.
Power consumption is measured with a sensor resistor between the
FPGA's ground and the board's ground.

The trace shows activity of the AES design very clearly but when there
is no operation performed, then there is almost no transient current
flow.

In our opinion, at least some activity due to the loading of the clock
tree should be visible.

I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
synthesizer generates some kind of power management for the design
(e.g. clock gating) so that there is nearly no power consumption, when
the design is not active? And if it does, is it possible to turn that
optimization behaviour off?

Best regards
Stefan Tillich