Virtex-6 XC6VHX380T Master SPI Configuration Problems....

[Jesper Kristensen]

Hello Group.

I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master
SPI loading problem.
Everything seems to go smoothely - Clock and Read command (0x03) is
given and the PROM returns data to DIN...
But loading never stops at the expected point, clock runs on and of
course no Config or Done is reached....

Thus - simple question:
Are there anybody here that have a working Master SPI loading of the
Virtex-6 XC6VHX380T or similar devices in the same family?

Bit data come out of the ISE 13.2 BitGen tool, which have been found
to suffer under this "feature":

- http://www.xilinx.com/support/answers/40920.htm

Currently, we are using these options:

-w
-g DebugBitstream:No
-g CRC:Enable
-g ConfigRate:2
-g CclkPinullUp
-g M0PinullUp
-g M1PinullUp
-g M2PinullUp
-g ProgPinullUp
-g InitPinullup
-g CsPinullup
-g DinPinullup
-g BusyPinullup
-g RdWrPinullup
-g HswapenPinullUp
-g TckPinullUp
-g TdiPinullUp
-g TdoPinullUp
-g TmsPinullUp
-g Disable_JTAG:No
-g UnusedPinullDown
-g UserID:0xFFFFFFFF
-g ConfigFallback:Enable
-g BPI_page_size:1
-g OverTempPowerDownisable
-g next_config_addr:0x00000000
-g JTAG_SysMon:Enable
-g DCIUpdateMode:Quiet
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g Match_cycle:Auto
-g Security:Level1
-g DonePipe:No
-g DriveDone:No
-g Binary:Yes


Are there anything else one should be focused on when setting the -g
"options"...?

Thanks in advance for your time & best regards,

Jesper.

 

[jwwebb]

On Sep 3, 5:14 am, Jesper Kristensen <repse...@gmail.com> wrote:

Hello Group.

I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master
SPI loading problem.
Everything seems to go smoothely - Clock and Read command (0x03) is
given and the PROM returns data to DIN...
But loading never stops at the expected point, clock runs on and of
course no Config or Done is reached....

Thus - simple question:
Are there anybody here that have a working Master SPI loading of the
Virtex-6 XC6VHX380T or similar devices in the same family?

Bit data come out of the ISE 13.2 BitGen tool, which have been found
to suffer under this "feature":

 -http://www.xilinx.com/support/answers/40920.htm

Currently, we are using these options:

-w
-g DebugBitstream:No
-g CRC:Enable
-g ConfigRate:2
-g CclkPinullUp
-g M0PinullUp
-g M1PinullUp
-g M2PinullUp
-g ProgPinullUp
-g InitPinullup
-g CsPinullup
-g DinPinullup
-g BusyPinullup
-g RdWrPinullup
-g HswapenPinullUp
-g TckPinullUp
-g TdiPinullUp
-g TdoPinullUp
-g TmsPinullUp
-g Disable_JTAG:No
-g UnusedPinullDown
-g UserID:0xFFFFFFFF
-g ConfigFallback:Enable
-g BPI_page_size:1
-g OverTempPowerDownisable
-g next_config_addr:0x00000000
-g JTAG_SysMon:Enable
-g DCIUpdateMode:Quiet
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g Match_cycle:Auto
-g Security:Level1
-g DonePipe:No
-g DriveDone:No
-g Binary:Yes

Are there anything else one should be focused on when setting the -g
"options"...?

Thanks in advance for your time & best regards,

  Jesper.

Hi Jesper,

Change the next_config_addr to this:

-g next_config_addr:None

That seemed to do the trick for me. Apparently, there was a bug in
13.1 and the bitgen options needed to be tweaked in order to generate
a good bit and mcs file.

Thanks,

Jeremy

 

[Jesper Kristensen]

On Sep 6, 3:09 am, jwwebb <jww...@jwebb-design.com> wrote:

On Sep 3, 5:14 am, Jesper Kristensen <repse...@gmail.com> wrote:









Hello Group.

I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master
SPI loading problem.
Everything seems to go smoothely - Clock and Read command (0x03) is
given and the PROM returns data to DIN...
But loading never stops at the expected point, clock runs on and of
course no Config or Done is reached....

Thus - simple question:
Are there anybody here that have a working Master SPI loading of the
Virtex-6 XC6VHX380T or similar devices in the same family?

Bit data come out of the ISE 13.2 BitGen tool, which have been found
to suffer under this "feature":

 -http://www.xilinx.com/support/answers/40920.htm

Currently, we are using these options:

-w
-g DebugBitstream:No
-g CRC:Enable
-g ConfigRate:2
-g CclkPinullUp
-g M0PinullUp
-g M1PinullUp
-g M2PinullUp
-g ProgPinullUp
-g InitPinullup
-g CsPinullup
-g DinPinullup
-g BusyPinullup
-g RdWrPinullup
-g HswapenPinullUp
-g TckPinullUp
-g TdiPinullUp
-g TdoPinullUp
-g TmsPinullUp
-g Disable_JTAG:No
-g UnusedPinullDown
-g UserID:0xFFFFFFFF
-g ConfigFallback:Enable
-g BPI_page_size:1
-g OverTempPowerDownisable
-g next_config_addr:0x00000000
-g JTAG_SysMon:Enable
-g DCIUpdateMode:Quiet
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g Match_cycle:Auto
-g Security:Level1
-g DonePipe:No
-g DriveDone:No
-g Binary:Yes

Are there anything else one should be focused on when setting the -g
"options"...?

Thanks in advance for your time & best regards,

  Jesper.

Hi Jesper,

Change the next_config_addr to this:

-g next_config_addr:None

That seemed to do the trick for me. Apparently, there was a bug in
13.1 and the bitgen options needed to be tweaked in order to generate
a good bit and mcs file.

Thanks,

Jeremy

Thanks a lot, Jeremy!
That did the trick for me, too!
As I suggested above, I was aware of this bitgen "flaw" and had
pointed it out to my IP vendor...
Unfortunately, they have only little experience with Xilinx, so they
thought they had their foot on it...
But that's life, I guess. ;-)

Thanks again - Jesper.