M
maxascent
Guest
I am using one of the built in fifo18 components and are having a smal
problem with the rst. I am using it in async mode and so would expect th
rst to be async. When I P&R the design in ISE 12.4 it tries to time th
reset to the rd clock. It uses the parameter Trrec_RST which I cant find i
the datasheet. Not sure if this is a bug or something I am missing.
Thanks
Jon
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Posted through http://www.FPGARelated.com
problem with the rst. I am using it in async mode and so would expect th
rst to be async. When I P&R the design in ISE 12.4 it tries to time th
reset to the rd clock. It uses the parameter Trrec_RST which I cant find i
the datasheet. Not sure if this is a bug or something I am missing.
Thanks
Jon
---------------------------------------
Posted through http://www.FPGARelated.com