Virtex 5 Rocket IO design for reading in ADC data.

J

jgk2004

Guest
Hello all,

I am presently working with a virtix 5 FPGA and trying to get the rocke
IOs to work with reading in the data generated from my ADC. The ADC i
clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my dat
4 bits transitioning at 250Mhz. I am then configuring the FPGA to store th
data after it has been serial to parallel converted within the FPGA then
read it out later after it has taken the data so I can process my FFT i
matlab. My problem is I know my ADC is working since I first took the dat
over a scope, but I want to speed up the measuring process by using a coo
and fancy FPGA. My question is, can any help me in setting up the rocke
IOs so ensure it does not miss any bits or transitions? If 1 in just 100
samples it wrong my FFT is completely crap and I cant use it!

My present setup, which I have no clue if I am correct, is I use th
rockets to sync to the incoming data (250MHz bits) only ( not the outpu
clock). I then use the same clock recovered for the data to then clock th
data into memory. My question is, is there a better way to do this? Cant
use my 500MHz clock to just clock the other data rocket IOs or since th
rocket IOs work off of a PLL, I cant do that.....

I feel this must be a standard thing in using the rocket IOs... I jus
don't have any clue on the proper setup. If anyone could help that woul
be great!



Jgk



---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello all,

I am presently working with a virtix 5 FPGA and trying to get the rocket
IOs to work with reading in the data generated from my ADC. The ADC is
clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and m
data
4 bits transitioning at 250Mhz. I am then configuring the FPGA to stor
the
data after it has been serial to parallel converted within the FPGA the
I
read it out later after it has taken the data so I can process my FFT in
matlab. My problem is I know my ADC is working since I first took th
data
over a scope, but I want to speed up the measuring process by using
cool
and fancy FPGA. My question is, can any help me in setting up the rocket
IOs so ensure it does not miss any bits or transitions? If 1 in just 1000
samples it wrong my FFT is completely crap and I cant use it!

My present setup, which I have no clue if I am correct, is I use the
rockets to sync to the incoming data (250MHz bits) only ( not the output
clock). I then use the same clock recovered for the data to then cloc
the
data into memory. My question is, is there a better way to do this? Can
i
use my 500MHz clock to just clock the other data rocket IOs or since the
rocket IOs work off of a PLL, I cant do that.....

I feel this must be a standard thing in using the rocket IOs... I just
don't have any clue on the proper setup. If anyone could help that would
be great!



Jgk



---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
I am slightly confused as you are talking about LVDS and Rocket IO whic
are not the same. Usually with ADC designs you would input the LVDS signal
from the ADC into the FPGA and use the ISERDES block clocked from the AD
clock. You may also have to use some soft of calibartion scheme involvin
an IDELAY block to ensure all bits are synchronised.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

I have output LVDS drive on my asic chip which I am then interfacing to th
rocket IOs of the FPGA. Sorry for the confusion. So you are saying tho
that I should not try any clock recoverary but just the clock from my asic
Is there anything else I would need to know to get this working properly?

Thanks so much

Jgk


Hello all,

I am presently working with a virtix 5 FPGA and trying to get the rocket
IOs to work with reading in the data generated from my ADC. The ADC is
clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my
data
4 bits transitioning at 250Mhz. I am then configuring the FPGA to store
the
data after it has been serial to parallel converted within the FPGA then
I
read it out later after it has taken the data so I can process my FFT in
matlab. My problem is I know my ADC is working since I first took the
data
over a scope, but I want to speed up the measuring process by using a
cool
and fancy FPGA. My question is, can any help me in setting up the rocket
IOs so ensure it does not miss any bits or transitions? If 1 in jus
1000
samples it wrong my FFT is completely crap and I cant use it!

My present setup, which I have no clue if I am correct, is I use the
rockets to sync to the incoming data (250MHz bits) only ( not the output
clock). I then use the same clock recovered for the data to then clock
the
data into memory. My question is, is there a better way to do this? Cant
i
use my 500MHz clock to just clock the other data rocket IOs or since the
rocket IOs work off of a PLL, I cant do that.....

I feel this must be a standard thing in using the rocket IOs... I just
don't have any clue on the proper setup. If anyone could help tha
would
be great!



Jgk



---------------------------------------
Posted through http://www.FPGARelated.com


I am slightly confused as you are talking about LVDS and Rocket IO which
are not the same. Usually with ADC designs you would input the LVD
signals
from the ADC into the FPGA and use the ISERDES block clocked from the ADC
clock. You may also have to use some soft of calibartion scheme involving
an IDELAY block to ensure all bits are synchronised.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

I have output LVDS drive on my asic chip which I am then interfacing t
the
rocket IOs of the FPGA. Sorry for the confusion. So you are saying thou
that I should not try any clock recoverary but just the clock from m
asic?
Is there anything else I would need to know to get this workin
properly?

Thanks so much

Jgk


Hello all,

I am presently working with a virtix 5 FPGA and trying to get th
rocket
IOs to work with reading in the data generated from my ADC. The ADC is
clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my
data
4 bits transitioning at 250Mhz. I am then configuring the FPGA to store
the
data after it has been serial to parallel converted within the FPG
then
I
read it out later after it has taken the data so I can process my FF
in
matlab. My problem is I know my ADC is working since I first took the
data
over a scope, but I want to speed up the measuring process by using a
cool
and fancy FPGA. My question is, can any help me in setting up th
rocket
IOs so ensure it does not miss any bits or transitions? If 1 in just
1000
samples it wrong my FFT is completely crap and I cant use it!

My present setup, which I have no clue if I am correct, is I use the
rockets to sync to the incoming data (250MHz bits) only ( not th
output
clock). I then use the same clock recovered for the data to then clock
the
data into memory. My question is, is there a better way to do this
Cant
i
use my 500MHz clock to just clock the other data rocket IOs or sinc
the
rocket IOs work off of a PLL, I cant do that.....

I feel this must be a standard thing in using the rocket IOs... I just
don't have any clue on the proper setup. If anyone could help that
would
be great!



Jgk



---------------------------------------
Posted through http://www.FPGARelated.com


I am slightly confused as you are talking about LVDS and Rocket IO which
are not the same. Usually with ADC designs you would input the LVDS
signals
from the ADC into the FPGA and use the ISERDES block clocked from th
ADC
clock. You may also have to use some soft of calibartion schem
involving
an IDELAY block to ensure all bits are synchronised.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com


---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
I am even more confused now as first you say you have an ADC and now yo
say an ASIC. I think you need to specify exactly what you have. Is it a
ADC from say TI or is it a custom ASIC chip? Rocket IO do not even use LVD
type signals so I dont really see what you are trying to do.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

I designed a custom ASIC sigma delta ADC and i do not decimate on chip. s
thus my data is coming out on 4 bits at 250MHz (clocked at 500MHz). On m
ASIC, i designed custom 1.2V LVDS drivers that need a 100ohm terminatio
off chip. I am using the rocket IOs and terminating them internally b
programming them to have 100Ohm termination. I then set the rocket IOs t
be lvds standard inputs.... which I think is correct to read in my data.
have to use the rocket IOs since my data is at 250MHz.....clocked a
500Mhz.. Am I doing anything wrong here? What type of signals would yo
normally use rocket IOs at... and even at high data rates.... I would thin
lvds type signals... Now what i think i am having trouble with is settin
up the syncing...

Is that alittle bit more clear?

Jgk



Hello Jon,

I have output LVDS drive on my asic chip which I am then interfacing to
the
rocket IOs of the FPGA. Sorry for the confusion. So you are saying thou
that I should not try any clock recoverary but just the clock from my
asic?
Is there anything else I would need to know to get this working
properly?

Thanks so much

Jgk


Hello all,

I am presently working with a virtix 5 FPGA and trying to get the
rocket
IOs to work with reading in the data generated from my ADC. The ADC is
clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my
data
4 bits transitioning at 250Mhz. I am then configuring the FPGA t
store
the
data after it has been serial to parallel converted within the FPGA
then
I
read it out later after it has taken the data so I can process my FFT
in
matlab. My problem is I know my ADC is working since I first took the
data
over a scope, but I want to speed up the measuring process by using a
cool
and fancy FPGA. My question is, can any help me in setting up the
rocket
IOs so ensure it does not miss any bits or transitions? If 1 in just
1000
samples it wrong my FFT is completely crap and I cant use it!

My present setup, which I have no clue if I am correct, is I use the
rockets to sync to the incoming data (250MHz bits) only ( not the
output
clock). I then use the same clock recovered for the data to then clock
the
data into memory. My question is, is there a better way to do this?
Cant
i
use my 500MHz clock to just clock the other data rocket IOs or since
the
rocket IOs work off of a PLL, I cant do that.....

I feel this must be a standard thing in using the rocket IOs... I just
don't have any clue on the proper setup. If anyone could help that
would
be great!



Jgk



---------------------------------------
Posted through http://www.FPGARelated.com


I am slightly confused as you are talking about LVDS and Rocket I
which
are not the same. Usually with ADC designs you would input the LVDS
signals
from the ADC into the FPGA and use the ISERDES block clocked from the
ADC
clock. You may also have to use some soft of calibartion scheme
involving
an IDELAY block to ensure all bits are synchronised.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com


---------------------------------------
Posted through http://www.FPGARelated.com


I am even more confused now as first you say you have an ADC and now you
say an ASIC. I think you need to specify exactly what you have. Is it an
ADC from say TI or is it a custom ASIC chip? Rocket IO do not even us
LVDS
type signals so I dont really see what you are trying to do.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

I designed a custom ASIC sigma delta ADC and i do not decimate on chip.
so
thus my data is coming out on 4 bits at 250MHz (clocked at 500MHz). O
my
ASIC, i designed custom 1.2V LVDS drivers that need a 100ohm termination
off chip. I am using the rocket IOs and terminating them internally by
programming them to have 100Ohm termination. I then set the rocket IO
to
be lvds standard inputs.... which I think is correct to read in my data.
I
have to use the rocket IOs since my data is at 250MHz.....clocked at
500Mhz.. Am I doing anything wrong here? What type of signals would you
normally use rocket IOs at... and even at high data rates.... I woul
think
lvds type signals... Now what i think i am having trouble with i
setting
up the syncing...

Is that alittle bit more clear?
Click to expand...
You would normally use Rocket IO for signals that are in the GHz range
LVDS on a Virtex 5 would easily handle a 250 MHz signal. Take a look at th
Xilinx website as they have some application notes on interfacing ADCs. Yo
do not want to be using Rocket IO for this type of application.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

So I do understand that 250MHz isn't fast, and the rocket IOs operate up t
3+GHz. The reason why I am using the rocket IOs now is because my next ASI
will be clocked at 1GHz to 1.5GHz.... So I was thinking if I can get th
rocket ios working at 250MHz it should be problem reprogramming them to
higher rate.

When you say that LVDS on the virtex 5 could easily be handled at 250MH
would I then need a core clock at above 250MHz? Also what is hte max LVD
could be used on the virtex 5 without the rocket IOs? Can i use LVDS a
1GHz?

Jgk



You would normally use Rocket IO for signals that are in the GHz range.
LVDS on a Virtex 5 would easily handle a 250 MHz signal. Take a look a
the
Xilinx website as they have some application notes on interfacing ADCs
You
do not want to be using Rocket IO for this type of application.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

So I do understand that 250MHz isn't fast, and the rocket IOs operate u
to
3+GHz. The reason why I am using the rocket IOs now is because my nex
ASIC
will be clocked at 1GHz to 1.5GHz.... So I was thinking if I can get the
rocket ios working at 250MHz it should be problem reprogramming them to a
higher rate.

When you say that LVDS on the virtex 5 could easily be handled at 250MHz
would I then need a core clock at above 250MHz? Also what is hte ma
LVDS
could be used on the virtex 5 without the rocket IOs? Can i use LVDS at
1GHz?

Jgk
Click to expand...
It seem to me as though you dont really understand the Virtex
architecture. You need to read the user guide and data sheet to get a fee
what is possible with a certain IO technology. Rocket IO uses CML typ
drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

You are completely correct, I do not understand the virtex 5 at all!!
What guide(since there are like 10) would you recommend reading to lear
about LVDS. Thank god i pinned out almost everything on my PCB t
headers... just need to make a new socket board!

Thanks

Jgk
It seem to me as though you dont really understand the Virtex 5
architecture. You need to read the user guide and data sheet to get
feel
what is possible with a certain IO technology. Rocket IO uses CML type
drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hello Jon,

You are completely correct, I do not understand the virtex 5 at all!!
What guide(since there are like 10) would you recommend reading to learn
about LVDS. Thank god i pinned out almost everything on my PCB to
headers... just need to make a new socket board!

Thanks

Jgk

It seem to me as though you dont really understand the Virtex 5
architecture. You need to read the user guide and data sheet to get a
feel
what is possible with a certain IO technology. Rocket IO uses CML type
drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com


---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
Just go to the Virtex 5 documentation page. There is the User Guide whic
will give you info about all the tech inside the fpga. The data sheet wil
tell you how fast things can go. I have just had a look on Xilinx and ther
is an app note called

Virtex-5 FPGA Interface to a JESD204A Compliant ADC

It looks like you can use Rocket IO if your ADC is compliant to JESD204A
standard. But as you have LVDS signals then you cant use this method.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Jun 30, 6:08 pm, "jgk2004"
<john.kauffman@n_o_s_p_a_m.n_o_s_p_a_m.uni-ulm.de> wrote:
Hello Jon,

You are completely correct,  I do not understand the virtex 5 at all!!
What guide(since there are like 10) would you recommend reading to learn
about LVDS.  Thank god i pinned out almost everything on my PCB to
headers... just need to make a new socket board!

Thanks

Jgk



It seem to me as though you dont really understand the Virtex 5
architecture. You need to read the user guide and data sheet to get a
feel
what is possible with a certain IO technology. Rocket IO uses CML type
drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible.

Jon    

---------------------------------------            
Posted throughhttp://www.FPGARelated.com

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
Go through the Virtex-5 user guide i.e. UG190. There is a detailed
chapter on SelectIO (Chapter 6) which will help you in serialization/
de-serialization of your 250MHz LVDS lines. One important point to be
noted here is that GTPs won't work at lower frequencies (You need to
use the oversampling circuitry available in GTPs) like 250 MHz in your
case. . Anyway GTPs work with HSTL standard which is different from
LVDS.
 
For our 5Gsps PCIe Digitizers we use a Virtex-5 to read ADC-Data at
1.25Gbps per pin.
We can see that we still have a few hundred ps of sampling window, so
1.5Gbps probably would work as well.

Virtex-6 or Virtex-6 should be able to do higher rates.

See xapp860.pdf and xapp855.pdf for more.

Kolja Sulimma
cronologic

On Jun 30, 12:43 pm, "jgk2004"
<john.kauffman@n_o_s_p_a_m.n_o_s_p_a_m.uni-ulm.de> wrote:
When you say that LVDS on the virtex 5 could easily be handled at 250MHz
would I then need a core clock at above 250MHz?  Also what is hte max LVDS
could be used on the virtex 5 without the rocket IOs? Can i use LVDS at
1GHz?
Click to expand...
 
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