M
maxascent
Guest
I am trying to debug a Virtex 5 PCI Express core. When I insert it into
PC it is not detecting it. I have chipscope connected to the LTSSM stat
machine signals and it seems to be stuck in state 2. Is there an
documentation from Xilinx that gives info about the states and the signal
that are exchanged during the link training?
Thanks
Jon
---------------------------------------
Posted through http://www.FPGARelated.com
PC it is not detecting it. I have chipscope connected to the LTSSM stat
machine signals and it seems to be stuck in state 2. Is there an
documentation from Xilinx that gives info about the states and the signal
that are exchanged during the link training?
Thanks
Jon
---------------------------------------
Posted through http://www.FPGARelated.com