Virtex 5 GTP Clocking

M

maxascent

Guest
Does anyone know if it is possible to drive a GTP tile with a clock from
PLL. I want to use the GREFCLK option and it says in the user guide tha
the CLKIN pin should be driven using a BUFG. I have done this with th
input of the BUFG from a PLL but when I try to map the design I get th
following error.

PhysDesignRules:2270 - Bloc
U_gtp_sata/tile0_v5_gtpwizard_v2_1_i/gtp_dual_i (GTP_DUAL_X0Y3) need
GTP_DUAL_X0Y2 instantiated: When using a GTP/GTX with a REFCLK coming fro
an IBUFDS element near another GTP/GTX, each GTP in between the source an
destination must be instantiated in the correct manner (See AR 33473). I
you don't instantiate these other GTP tiles the software tools will rout
the REFCLK correctly, but the design may not work in hardware.

It may be that you can only drive the BUFG from an external clock but
would be interested if anyone knows this for certain.

Thanks

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
I don't know if PLL is allowed as a clock source, but the error you see
seems to me unrelated. It simply says that the tiles in path of the clock
have to be powered up, or else there is no guarantee that they will pass
clock properly.

With regards to using PLL, look at jitter/phase noise requirements of the
GTP/GTX and see if they can be met when the PLL is used.

/Mikhail



"maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote in message
news:96adnflEw6DZAFjRnZ2dnUVZ_vudnZ2d@giganews.com...
Does anyone know if it is possible to drive a GTP tile with a clock from a
PLL. I want to use the GREFCLK option and it says in the user guide that
the CLKIN pin should be driven using a BUFG. I have done this with the
input of the BUFG from a PLL but when I try to map the design I get the
following error.

PhysDesignRules:2270 - Block
U_gtp_sata/tile0_v5_gtpwizard_v2_1_i/gtp_dual_i (GTP_DUAL_X0Y3) needs
GTP_DUAL_X0Y2 instantiated: When using a GTP/GTX with a REFCLK coming from
an IBUFDS element near another GTP/GTX, each GTP in between the source and
destination must be instantiated in the correct manner (See AR 33473). If
you don't instantiate these other GTP tiles the software tools will route
the REFCLK correctly, but the design may not work in hardware.

It may be that you can only drive the BUFG from an external clock but I
would be interested if anyone knows this for certain.

Thanks

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
I think the error is just a generic error message. I'm not too bothere
about jitter at the moment as I wont be using the GREFCLK in the fina
design. The board I am using doesnt have a clk on the GTP clk inputs so
needed to find another way to get a clk.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 

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