M
maxascent
Guest
Does anyone know if it is possible to drive a GTP tile with a clock from
PLL. I want to use the GREFCLK option and it says in the user guide tha
the CLKIN pin should be driven using a BUFG. I have done this with th
input of the BUFG from a PLL but when I try to map the design I get th
following error.
PhysDesignRules:2270 - Bloc
U_gtp_sata/tile0_v5_gtpwizard_v2_1_i/gtp_dual_i (GTP_DUAL_X0Y3) need
GTP_DUAL_X0Y2 instantiated: When using a GTP/GTX with a REFCLK coming fro
an IBUFDS element near another GTP/GTX, each GTP in between the source an
destination must be instantiated in the correct manner (See AR 33473). I
you don't instantiate these other GTP tiles the software tools will rout
the REFCLK correctly, but the design may not work in hardware.
It may be that you can only drive the BUFG from an external clock but
would be interested if anyone knows this for certain.
Thanks
Jon
---------------------------------------
Posted through http://www.FPGARelated.com
PLL. I want to use the GREFCLK option and it says in the user guide tha
the CLKIN pin should be driven using a BUFG. I have done this with th
input of the BUFG from a PLL but when I try to map the design I get th
following error.
PhysDesignRules:2270 - Bloc
U_gtp_sata/tile0_v5_gtpwizard_v2_1_i/gtp_dual_i (GTP_DUAL_X0Y3) need
GTP_DUAL_X0Y2 instantiated: When using a GTP/GTX with a REFCLK coming fro
an IBUFDS element near another GTP/GTX, each GTP in between the source an
destination must be instantiated in the correct manner (See AR 33473). I
you don't instantiate these other GTP tiles the software tools will rout
the REFCLK correctly, but the design may not work in hardware.
It may be that you can only drive the BUFG from an external clock but
would be interested if anyone knows this for certain.
Thanks
Jon
---------------------------------------
Posted through http://www.FPGARelated.com