Virtex-5 clocking

[Saul Bernstein]

Hi Folks,



altough brand new I hope someone already made some experience with Virtex-5.
I just switched from Virtex-4 to Virtex-5 and I must admit that the clock
managment is... and remains... somewhat unclear to me!

It's plain to see that the clock management is handled a bit differently
than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers)
technology for delay control and PLL (phased lock loop) technology for lower
jitter clock generation. But what does that mean to me, practically? What
should I account for when designing a PCB with Virtex-5? Which IOs am I
supposed to use?

In Virtex-4 I had Global Clock and Regional Clock Inputs. So far so good. In
Virtex-5 I have plenty of different clock inputs and it is almost impossible
to arrange for an optimal clock management at the time prior to developing
the internal VHDL logic for the FPGA. Basically I'd like to know how to
connect my global clock sources to the FPGA without catching problems later
in implementing the VHDL and getting confronted with timing errors, etc.

Same problem - still much worse - with the RocketIO reference clocks! Plenty
of clock inputs but. much too confusing! For example I'd like to take one
reference clock for an arrangement of 10 RocketIOs. No problem with
Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 for the
clocks can only supply 4 RocketIOs at once... as far as I can judge.



Still, I may be wrong! So any help is highly appreciated.



Saul

 

[Ed McGettigan]

Saul Bernstein wrote:

Same problem - still much worse - with the RocketIO reference clocks! Plenty
of clock inputs but. much too confusing! For example I'd like to take one
reference clock for an arrangement of 10 RocketIOs. No problem with
Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 for the
clocks can only supply 4 RocketIOs at once... as far as I can judge.

The Virtex-5 MGT REFCLK inputs can span up and down 3 of the GTP_DUAL or
GTX_DUAL sites, so you can reach 7 DUALs or 14 lanes.

Ed McGettigan
--
Xilinx Inc.

 

[Saul Bernstein]

Alright then.7 DUALs means 7 RocketIOs with both RX and TX connected, i.e.
14 lanes? In my application I'd like to have 10 MGTs (both RX + TX) running
at 3.125 Gbps, 4 running at 5 Gbps, 2 at 4.25 Gbps and another 4 running at
2.5 Gbps. Which RocketIOs would you recommend to combine, relating to a
shared reference MGTCLK input?

While we're at it, I've got another question concerning the power supply. On
the ML510 eval platform Xilinx used seperate 1.0V supply modules for every
MGT reference voltage input. That looks quite exaggerated to me. Is that a
mandatory requirement?

Saul



"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag
news:_MrHk.2845$as4.166@nlpi069.nbdc.sbc.com...

Saul Bernstein wrote:

Same problem - still much worse - with the RocketIO reference clocks!
Plenty of clock inputs but. much too confusing! For example I'd like to
take one reference clock for an arrangement of 10 RocketIOs. No problem
with Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5
for the clocks can only supply 4 RocketIOs at once... as far as I can
judge.


The Virtex-5 MGT REFCLK inputs can span up and down 3 of the GTP_DUAL or
GTX_DUAL sites, so you can reach 7 DUALs or 14 lanes.

Ed McGettigan
--
Xilinx Inc.

 

[Gabor]

On Oct 10, 8:25 am, "Saul Bernstein" <jiffyl...@freenet.de> wrote:
[snip]

While we're at it, I've got another question concerning the power supply. On
the ML510 eval platform Xilinx used seperate 1.0V supply modules for every
MGT reference voltage input. That looks quite exaggerated to me. Is that a
mandatory requirement?

Saul

The eval board is somewhat overkill. The general rule is to place
a filter from a clean 1.0V supply (not the Vccint supply) to each
of the MGT blocks used. Unused MGT blocks also need to
be powered, but don't require a filter.

Also you should have two 1.2V supplies, one for the VTT pins
and one for PLL supplies. Again every MGT VTT and PLL pin
need a filter when used.

My filters consist of a ferrite bead with about 220 Ohms
at 100 MHz - BLM21PG221SN1 from Murata, and a
0.22 uF capacitor. I used 0508 low esr ceramics with
leads on the long edges of the part, and two vias per
pad. This may be overkill, but it didn't cost too much
in board space and the results were good. Note that
the V5 in the larger packages (which you must have
if you've got 10 GTP's) have a lot of internal bypass
caps, so you should have room for the MGT bypass
given that the other supply high-frequency bypass is
mostly in the BGA package.

Regards,
Gabor

 

[Ed McGettigan]

Saul Bernstein wrote:

Alright then.7 DUALs means 7 RocketIOs with both RX and TX connected, i.e.
14 lanes? In my application I'd like to have 10 MGTs (both RX + TX) running
at 3.125 Gbps, 4 running at 5 Gbps, 2 at 4.25 Gbps and another 4 running at
2.5 Gbps. Which RocketIOs would you recommend to combine, relating to a
shared reference MGTCLK input?

While we're at it, I've got another question concerning the power supply. On
the ML510 eval platform Xilinx used seperate 1.0V supply modules for every
MGT reference voltage input. That looks quite exaggerated to me. Is that a
mandatory requirement?

Saul



"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag
news:_MrHk.2845$as4.166@nlpi069.nbdc.sbc.com...
Saul Bernstein wrote:
Same problem - still much worse - with the RocketIO reference clocks!
Plenty of clock inputs but. much too confusing! For example I'd like to
take one reference clock for an arrangement of 10 RocketIOs. No problem
with Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5
for the clocks can only supply 4 RocketIOs at once... as far as I can
judge.

The Virtex-5 MGT REFCLK inputs can span up and down 3 of the GTP_DUAL or
GTX_DUAL sites, so you can reach 7 DUALs or 14 lanes.

Ed McGettigan
--
Xilinx Inc.

A GTP_DUAL site in Virtex-5 is the equivalent of 2 MGTs in the V-II Pro
and V-4 FX families, so 7 GTP_DUALs is 14 MGTs, 4 more than you need.
Any 5 adjacent GTP_DUALs will meet your needs and use the REFCLK in on
the sites in the middle so that you don't violate the +/- 3 GTP_DUAL
requirement.

The ML510 does not have separate power supplies for each GTP_DUAL, but
it does have separate power supplies for each voltage rail, AVCC
AVCC_PLL, AVCC, AVTT_TX and AVTT_RX. We did it this way so that we
could margin the voltage rails independently if there was a need.

Ed McGettigan
--
Xilinx Inc.

 

Le jeudi 9 octobre 2008 18:18:30 UTC+1, Saul Bernstein a écrit :

Hi Folks,



altough brand new I hope someone already made some experience with Virtex-5.
I just switched from Virtex-4 to Virtex-5 and I must admit that the clock
managment is... and remains... somewhat unclear to me!

It's plain to see that the clock management is handled a bit differently
than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers)
technology for delay control and PLL (phased lock loop) technology for lower
jitter clock generation. But what does that mean to me, practically? What
should I account for when designing a PCB with Virtex-5? Which IOs am I
supposed to use?

In Virtex-4 I had Global Clock and Regional Clock Inputs. So far so good. In
Virtex-5 I have plenty of different clock inputs and it is almost impossible
to arrange for an optimal clock management at the time prior to developing
the internal VHDL logic for the FPGA. Basically I'd like to know how to
connect my global clock sources to the FPGA without catching problems later
in implementing the VHDL and getting confronted with timing errors, etc.

Same problem - still much worse - with the RocketIO reference clocks! Plenty
of clock inputs but. much too confusing! For example I'd like to take one
reference clock for an arrangement of 10 RocketIOs. No problem with
Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 for the
clocks can only supply 4 RocketIOs at once... as far as I can judge.



Still, I may be wrong! So any help is highly appreciated.



Saul