Virtex 2 Pro OCM question

[MS]

We are using a V2Pro with the embedded PowerPC. We have several
packet queues that go back and forth between the processor and the
custom fast path logic. We have decided to implement these in Data
OCM block memories.

The issue we are having is that when we goto add a DSOCM- it generates
one memory (not necessary one block memory)- with Port A going to the
DSOCM IF and port B going to the logic. This is great for one queue-
but doesn't work for multiple queues.

We then looked at the generated code (HDL directory of our project)
and figure we can edit the dsocm_bram_elaborate and wrapper to do what
we want. This should be fine- but whenever we change the MHS file
and/or compile it- it will write over these changes. The process
would become more manual.

We would like to be able to edit this blockRam so that the MHS file
references this. I looked in the EDK/hw/XilinxProcessorIP/pcores
directory at the bram block- and there is no HDL to edit.

Has anyone else done something similar? I have a few paths I want to
go down- but if anyone can eliminate or suggest one I am all ears. My
next thing will be to edit a copy of the dsbram_if_cntl HDL and plop a
few block Memories directly into it and see if this works- but again-
I am open to suggestions.

 

[Paulo Dutra]

Yes, this is possible.

There's no HDL in the hdl directory as the bram_block is generated
on the fly.

Depending on how you modified the dsocm_bram_elaborate. It sounds
like you introduced user logic. This may be better partitioned
as it's own pcore. This way you allow the tools to regenerate
bram_block.

You can send me email paulo_dutra@xilinx_com (replace all "_" with ".")
for more details.

MS wrote:

We are using a V2Pro with the embedded PowerPC. We have several
packet queues that go back and forth between the processor and the
custom fast path logic. We have decided to implement these in Data
OCM block memories.

The issue we are having is that when we goto add a DSOCM- it generates
one memory (not necessary one block memory)- with Port A going to the
DSOCM IF and port B going to the logic. This is great for one queue-
but doesn't work for multiple queues.

We then looked at the generated code (HDL directory of our project)
and figure we can edit the dsocm_bram_elaborate and wrapper to do what
we want. This should be fine- but whenever we change the MHS file
and/or compile it- it will write over these changes. The process
would become more manual.

We would like to be able to edit this blockRam so that the MHS file
references this. I looked in the EDK/hw/XilinxProcessorIP/pcores
directory at the bram block- and there is no HDL to edit.

Has anyone else done something similar? I have a few paths I want to
go down- but if anyone can eliminate or suggest one I am all ears. My
next thing will be to edit a copy of the dsbram_if_cntl HDL and plop a
few block Memories directly into it and see if this works- but again-
I am open to suggestions.

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