viewing signals and ports all the way down

[John Bleichert]

Greetings

I'm using NC-Sim to compile and simulate a pure VHDL design. There are
5 layers to the hierarchy, but no matter how I set access during
elaboration I can only see signal and port values and waveforms for
the top piece of logic. I've tried setting the scope but this has led
to, at best, confusing results.

Is there any quick and dirty way to set NC-Sim to show waverforms and
signal data for *all* signals and ports everywhere in the design
hierarchy? I thought that's what "-access +r" was suppoed to do as an
arg to ncelab?

Any help or doc pointer appreciated - I've been over and over the docs
for probe, access and scope and can't seem to get it.

Thanks - JB



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John Bleichert - syborg@earthlink.net
"The meek shall inherit nothing." - FZ