Viewing multi-dimensional arrays in Simvision

[Jal]

[POSTED to .cad.cadence and .lang.verilog]

Hi,

Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.

I couldn't get NC-verilog to compile the following bit of code.

//4*4 array of byte
wire [7:0] my_array [1:0] [1:0];

So, instead, I used a 'reg', and this compiled OK,

//4*4 array of byte
reg [7:0] my_array [1:0] [1:0];

BUT, when I simulate my design, and open my .trn file in Simvision
(also tried signalscan), I can't seem to see any of my
multi-dimensional signals. I even tried a simple memory like this:

reg [7:0] mem [0:1023].

and even this was not displayed in the "signal/Variables of scope"
window.

Can these tools not display multi-dimensional arrays, or do I have to
set some kind of option somewhere?

p.s I am new to Verilog (ex-VHDL) and the Cadence toolset.

thanks,
Jal.

 

[Ajeetha Kumari]

Hi Jal,
Which version are you using? I used to use 5.1 and that supported
memory displays in waveform seamlessly, use the source browser to
locate the memory declaration and then you can send that memory to
waveform.

$CDS_INST_DIR/doc/simvision/displaying.html should have the needed
documentaion for it.

Regards,
Ajeetha
http://www.noveldv.com

jalibahmed@hotmail.com (Jal) wrote in message news:<d8e046e.0410050036.3fbae8ee@posting.google.com>...

Hi,

Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.

I couldn't get NC-verilog to compile the following bit of code.

//4*4 array of byte
wire [7:0] my_array [1:0] [1:0];

So, instead, I used a 'reg', and this compiled OK,

//4*4 array of byte
reg [7:0] my_array [1:0] [1:0];

BUT, when I simulate my design, and open my .trn file in Simvision
(also tried signalscan), I can't seem to see any of my
multi-dimensional signals. I even tried a simple memory like this:

reg [7:0] mem [0:1023].

and even this was not displayed in the "signal/Variables of scope"
window.

Can these tools not display multi-dimensional arrays, or do I have to
set some kind of option somewhere?

p.s I am new to Verilog (ex-VHDL) and the Cadence toolset.

thanks,
Jal.

 

Hello Jal

Are you probing the signals to get the waveform?
because if you are then you can dump two dimensional array using $shm_probe("ACTM") (where M is for memory) in your testbench top.

Following is the document that you can refer (page no 657)

http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=4124662530AB55B5B551CA0005E39C0C?doi=10.1.1.433.1841&rep=rep1&type=pdf

Ashish