Viewing internal signals with ModelSim

[Joseph]

Hi all,

I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
only displays the input/output signals of the simulated top entity.

Is there a way of viewing the internal signals declared in the
architecture of the entity without adding them to the port outputs of
the simulated top entity?

Thanks very much

Regards

Joseph

 

[HT-Lab]

"Joseph" <jozamm@gmail.com> wrote in message
news:12d475c1-5c84-48fd-8ef3-c49357b06f42@2g2000hsn.googlegroups.com...

Hi all,

I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
only displays the input/output signals of the simulated top entity.

Is there a way of viewing the internal signals declared in the
architecture of the entity without adding them to the port outputs of
the simulated top entity?

Thanks very much

Regards

Joseph

Modelsim will optimise your design by default and hence you might loose some
internal signals, try "log -r *" before running your simulation.

Hans
www.ht-lab.com

 

[David R Brooks]

Joseph wrote:

Hi all,

I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
only displays the input/output signals of the simulated top entity.

Is there a way of viewing the internal signals declared in the
architecture of the entity without adding them to the port outputs of
the simulated top entity?

Sorry if this is obvious, but you have tried descending the hierarchy in

the "Workspace" window? Signals at the current level are listed in
"Objects", & you can add them to the display.

 

[Kevin Neilson]

Joseph wrote:

Hi all,

I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
only displays the input/output signals of the simulated top entity.

Is there a way of viewing the internal signals declared in the
architecture of the entity without adding them to the port outputs of
the simulated top entity?

Thanks very much

Regards

Joseph

I don't know if this will help you, but I've noticed that the new
version of Modelsim optimizes away internal signals by default. I have
to use a new argument in vsim:

vsim -voptargs="+acc" test

-Kevin