Via in Hyperlynx linesim

[Mark]

Is there anyway to specify via in HyperLynx LineSim? For example, I
have a transmission line with microstrip of length 20mm on top layer ,
then goes through a via to inner layer for microstrip and again
through another via back to top layer before going to the receiver. I
want simulate this in Hyperlynx LineSim but doesn't know how to
specify in the LineSim schematic.

-mark

 

[KJ]

On Mar 22, 11:47 am, Mark <markjsu...@gmail.com> wrote:

Is there anyway to specify via in HyperLynx LineSim? For example, I
have a transmission line with microstrip of length 20mm on top layer ,
then goes through a via to inner layer for microstrip and again
through another via back to top layer before going to the receiver. I
want simulate this in Hyperlynx LineSim but doesn't know how to
specify in the LineSim schematic.

Create a PCB stackup and then make your net in Linesim by having
segments of that net travel on whatever PCB layers you want (i.e. 1
inch on Layer 1; 1.5 inch on Layer 2; 0.5 inch on Layer 1 again).

KJ

 

[Mark]

On Mar 22, 9:38 pm, KJ <kkjenni...@sbcglobal.net> wrote:

On Mar 22, 11:47 am, Mark <markjsu...@gmail.com> wrote:

Is there anyway to specify via in HyperLynx LineSim? For example, I
have a transmission line with microstrip of length 20mm on top layer ,
then goes through a via to inner layer for microstrip and again
through another via back to top layer before going to the receiver. I
want simulate this in Hyperlynx LineSim but doesn't know how to
specify in the LineSim schematic.

Create a PCB stackup and then make your net in Linesim by having
segments of that net travel on whatever PCB layers you want (i.e. 1
inch on Layer 1; 1.5 inch on Layer 2; 0.5 inch on Layer 1 again).

KJ

Thanks KJ. I quickly created a simple LineSim schematic for this
clarification. Please find it at the link below.
https://picasaweb.google.com/115209162259670831525/MyAlbum?authkey=Gv1sRgCPjvkPjw26WhPQ#

In the screen shot at the link above, there should be a via from
Microstrip to Stripline (top layer to inner layer) and again from
Stripline to Microstrip (inner layer to top layer). How do I specify
that? Does HyperLynx automatically assumes via from Microstrip to
Stripline and from Stripline to Microstrip? If Yes, via size doesn't
have any impact on SI?

-mark