via doubling

[manjunath]

Hi

Can anybody tell me how double vias will be inserted (to improve
yield) in designs by scripts?
Is it done using only skill or any physical verification tool along
with skill ( for eg: skill and assura)

Thanks and regards
Manjunath

 

[gerry@ictooling.com]

manjunath wrote:

Hi

Can anybody tell me how double vias will be inserted (to improve
yield) in designs by scripts?
Is it done using only skill or any physical verification tool along
with skill ( for eg: skill and assura)

Thanks and regards
Manjunath

Simplistically, the tool will "look" for isolated via structures that
are yield limiting.
Any of these structures that also have the resources (i.e. area another
via and extra metal)
are targets for improvement.

(I have modified entire STD Cell libraries to double all the Contacts
by hand and created
Encounter decks that only recognize double via structures. This is the
other way of attacking
this with the liberal use of more space.)

-- Gerry

 

[gerry@ictooling.com]

manjunath wrote:

Hi

Can anybody tell me how double vias will be inserted (to improve
yield) in designs by scripts?
Is it done using only skill or any physical verification tool along
with skill ( for eg: skill and assura)

Thanks and regards
Manjunath

Simplistically, the tool will "look" for isolated via structures that
are yield limiting.
Any of these structures that also have the resources (i.e. area another
via and extra metal)
are targets for improvement.

(I have modified entire STD Cell libraries to double all the Contacts
by hand and created
Encounter decks that only recognize double via structures. This is the
other way of attacking
this with the liberal use of more space.)

-- Gerry

 

[Andrew Beckett]

On 10 Dec 2006 21:47:51 -0800, "manjunath" <manjunath.pai@gmail.com> wrote:

Hi

Can anybody tell me how double vias will be inserted (to improve
yield) in designs by scripts?
Is it done using only skill or any physical verification tool along
with skill ( for eg: skill and assura)

Thanks and regards
Manjunath

There's also a Cadence tool called the Cadence Chip Optimizer which will do this
(plus other yield optimisation type things).

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.