VHDLIn in Cadence

Hi all,

I have copied the full adder design from "Guide to VHDL In for Design
Framework II" and imported the vdhl code into cadence to generate a
schematic. But I am not sure how I would simulate that schematic (there
is no stimuli). I have tried a couple things but they keep giving me
errors like cannot decent into behavior cellview (while the view is
there). I was wondering if anyone out there can tell me how you
simulated using AMS.

Thanks