VHDL

[Repzak]

Hey

i am pretty green at this VHDL...

can someone tell me the error in this code.. :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;


entity Test is
port(
b: in std_logic;
a: out std_logic_vector(7 downto 0));
end Test;


architecture eksempel of Test is
signal a_old,a_new : std_logic_vector(7 downto 0);
begin


test_ifrocess(b)
begin

if b='1' then
a_new <= a_old + 1;
end if;
a<=a_new;
end process test_if;

end eksempel;


it was suposed to add 1 to A

regards Kasper

 

[Michael Schöberl]

can someone tell me the error in this code.. :
[...]
it was suposed to add 1 to A

I would say your code adds 1 to a_old ... your
problems are:

- a_old is not set ... there is no startup-init nor any
other assignment

- what should be the output of A if b = '0' ??
you need a flipflop description for a counter
if rising_edge(b)
a_out <= a_out + 1;
end if;


there are many tutorials on the web ... perhaps you
should read one ...

thinking in "hardware" is very different from sequential
programming - you need to learn that for vhdl ...


bye,
Michael

 

[Don Golding]

I believe that the phrase:
a_new <= a_old + 1;
should be:
a_new <= a_old + "0000001";

Didn't check the rest...
Doesn't he need the use list the IEEE.STD_LOGIC_ARITH.all; too?

Don

"Repzak" <repzak@GEDhotmail.com> wrote in message
news:4102799b$0$66476$14726298@news.sunsite.dk...

Hey

i am pretty green at this VHDL...

can someone tell me the error in this code.. :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;


entity Test is
port(
b: in std_logic;
a: out std_logic_vector(7 downto 0));
end Test;


architecture eksempel of Test is
signal a_old,a_new : std_logic_vector(7 downto 0);
begin


test_ifrocess(b)
begin

if b='1' then
a_new <= a_old + 1;
end if;
a<=a_new;
end process test_if;

end eksempel;


it was suposed to add 1 to A

regards Kasper

 

[Repzak]

there are many tutorials on the web ... perhaps you
should read one ...

Hey...

Thats defentlig true...

i also have some books and some urls, but a lot to take care of in the first
place

i need more some simple code... btw i am using protel / nexar...

but there are so much to read, i need to get going a litle to try and read
and try...

i think i got some of the problems...

my next is pushbutton bouncing... ):

Kasper

 

[C]

"Don Golding" <dgolding@sbcglobal.net> wrote in message
news:KBAMc.96743$9g3.68705@newssvr29.news.prodigy.com...

I believe that the phrase:
a_new <= a_old + 1;
should be:
a_new <= a_old + "0000001";

Didn't check the rest...
Doesn't he need the use list the IEEE.STD_LOGIC_ARITH.all; too?

Don

"Repzak" <repzak@GEDhotmail.com> wrote in message
news:4102799b$0$66476$14726298@news.sunsite.dk...
Hey

i am pretty green at this VHDL...

can someone tell me the error in this code.. :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;


entity Test is
port(
b: in std_logic;
a: out std_logic_vector(7 downto 0));
end Test;


architecture eksempel of Test is
signal a_old,a_new : std_logic_vector(7 downto 0);
begin


test_ifrocess(b)
begin

if b='1' then
a_new <= a_old + 1;
end if;
a<=a_new;
end process test_if;

end eksempel;


it was suposed to add 1 to A

regards Kasper

I think that's the problem as well. You could use:

a_new <= a_old + '1'; -- note the ' '

You really want some sort of reset. Also, you can just use a single signal
to hold the temporary A value (I have called it a_sig). You can then change
your process to read:

test_if: process(b)
begin
if b'event and b = '1' then -- rising edge of b
if RST = '0' then
a_sig <= (others => '0'); -- make a_sig all zeros
else
a_sig <= a_sig + '1'; -- increment a_sig
end if;
end if;
end process test_if;

a <= a_sig; -- put this line outside of your process (a will always
equal a_sig).


Hope that helps.