VHDL warning " Feedback mux " from synplify pro ...thx

[Jimmy]

Hi, all ,
I use syplify to synthesize the following vhdl. it comes out with
warnings for signal BitSync_temp, pnt. It seems from the coding logic it
can't have the mux problem since the assignment conditions exclude each
other...(to my understanding), could you give me some comments , thanks
first.

Warning:
@W: CL113 : Feedback mux created for signal BitSync_temp.
@W: CL113 : Feedback mux created for signal pnt[6:0].

process(Clk, Reset,MaxSearchEn)
variable pnt : std_logic_vector(6 downto 0); -- integer range 87 downto
0; 88= 101 1000
begin
if (Reset = '1') then
pnt := (others => '0');
BitSync_temp <= '0';
....
elsif (Clk'event and Clk = '1' and MaxSearchEn = '1') then

....

if (pnt < "1011000") then
pnt := pnt + '1';
else
pnt := (others => '0');

if (PeakValue(BitWidth+6 downto 3) >= "011111111111" ) then
BitSync_temp <= '1';
else
BitSync_temp <= '0';
end if;

end if;

end if;
end process;

regards,
Jimmy

 

[Allan Herriman]

On Mon, 31 May 2004 17:18:57 +0800, "Jimmy" <mljiang@eee.hku.hk>
wrote:

process(Clk, Reset,MaxSearchEn)

change to

process(Clk, Reset)

You don't really want the process sensitive to events on MaxSearchEn,
I assume that signal is meant to be a clock enable.

Regards,
Allan.

 

[Allan Herriman]

On Mon, 31 May 2004 19:53:44 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Mon, 31 May 2004 17:18:57 +0800, "Jimmy" <mljiang@eee.hku.hk
wrote:

process(Clk, Reset,MaxSearchEn)

change to

process(Clk, Reset)

You don't really want the process sensitive to events on MaxSearchEn,
I assume that signal is meant to be a clock enable.

Also, your clock enabled processes should look something like:

label : process(clk, reset)
begin
if reset = '1' then
...
elsif rising_edge(clk) then
if clk_enable = '1' then
...
end if;
end if;
end process;

Comments:
1. You don't need () around the condition in an IF statement. You're
not writing C (or Verilog)!

2. rising_edge(clk) is a lot clearer than clk'event and clk='1'.
There are some minor semantic differences that probably won't worry
you.

3. Use separate IF statements for the rising_edge and clk_enable
parts. It's easier to read, and some synthesisers may have problems
if they're combined into the one condition.

4. VHDL doesn't force you to label processes, but I find it makes it
easier to read the code if they are labeled, assuming you choose
labels sensibly.

Regards,
Allan.

 

[Ray Andraka]

The feedback mux warning comes about because of the condition where
bitsync_temp is not assigned in the if_then potion:

Jimmy wrote:

if (pnt < "1011000") then
pnt := pnt + '1';
else
pnt := (others => '0');

if (PeakValue(BitWidth+6 downto 3) >= "011111111111" ) then
BitSync_temp <= '1';
else
BitSync_temp <= '0';
end if;

end if;

That structure makes an implied memory element for bitsync_temp in the case
pnt<"1011000". separate the logic for pnt and bitSync_temp into two separate
if then elses to fix the problem as well as to make it more readable.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

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