VHDL vs Verilog

[Rob]

I'm sure this question has been addressed on this newsgroup many times in
the past, so it should be easy to cut and paste a response

I've read that Verilog is an easier language to learn; and from some of the
posts on this group it also would seem that Verilog has some nice features
that VHDL doesn't. So, my question is simply, does one language offer a
major advantage over the other, and if so why?

Take care,
Rob

 

[Mike Treseler]

Rob wrote:

I'm sure this question has been addressed on this newsgroup many times in
the past, so it should be easy to cut and paste a response

here you go:
http://groups.google.com/groups?q=vhdl+vs+verilog

 

[Jos De Laender]

Rob wrote:

I'm sure this question has been addressed on this newsgroup many times in
the past, so it should be easy to cut and paste a response

I've read that Verilog is an easier language to learn; and from some of the
posts on this group it also would seem that Verilog has some nice features
that VHDL doesn't. So, my question is simply, does one language offer a
major advantage over the other, and if so why?

Take care,
Rob

For this one you *really* should use google.
Chances that additional arguments pro or contra are still collected here
are nihil

 

[Jonathan Bromley]

On Sun, 09 Oct 2005 09:53:24 GMT, Jos De Laender
<VarkensVoer@hotmail.com> wrote:

Chances that additional arguments pro or contra are still collected here
are nihil

Sure, but it's still fun to have a rant during your coffee break...
--
Jonathan Bromley, Consultant

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