VHDL vs. Verilog

[Pawel]

Hello All

Can anybody give me link to the discussion on
advantages and disadvantages on using VHDL and
Verilog?
The selection should be constrained only to the
digital hardware.

Thanks in advance
Pawel

 

[Pawel]

This sort of Holy War has been fought since the dawn of time. I'm sure
Googling for "VHDL vs Verilog" will barely skim the surface.

Exactly, I got so many answers that I would drown in this. Tharefore I
wanted to get an opinion from the group.
There must be some advantages of using one of them to dsp.

cheers
Pawel

 

[Jason Zheng]

Pawel wrote:

Hello All

Can anybody give me link to the discussion on
advantages and disadvantages on using VHDL and
Verilog?
The selection should be constrained only to the
digital hardware.

Thanks in advance
Pawel
That's just the perfect flame bait for slashdot, .

 

[B. Joshua Rosen]

On Tue, 19 Jul 2005 15:24:05 +0200, Pawel wrote:

This sort of Holy War has been fought since the dawn of time. I'm sure
Googling for "VHDL vs Verilog" will barely skim the surface.

Exactly, I got so many answers that I would drown in this. Tharefore I
wanted to get an opinion from the group.
There must be some advantages of using one of them to dsp.

cheers
Pawel

This really is a religious issue. I'll give you the my reason for
preferring Verilog, it's much more concise. Verilog is is concise, VHDL is
horribly verbose so Verilog code is much much easier to read and write.

 

[Heelothere]

"soxmax" <soxmax_2000@yahoo.com> wrote in message
news:1121794194.489414.19380@g49g2000cwa.googlegroups.com...

It is my experience that Government likes VHDL while the commercial
industry likes Verilog. Given the choice I would probably always use
Verilog. You can go to opencores.org and see what they have to offer -
this may help you make your choice.

Perhaps in the US. (US Educational institutions, those funded for
academic research, also slant heavily towards VHDL.) In Europe, VHDL
has greater overall popularity.

 

[Andy Peters]

Pawel wrote:

Hello All

Can anybody give me link to the discussion on
advantages and disadvantages on using VHDL and
Verilog?
The selection should be constrained only to the
digital hardware.

This sort of Holy War has been fought since the dawn of time. I'm sure
Googling for "VHDL vs Verilog" will barely skim the surface.

-a

 

[soxmax]

Pawel wrote:

Hello All

Can anybody give me link to the discussion on
advantages and disadvantages on using VHDL and
Verilog?
The selection should be constrained only to the
digital hardware.

Thanks in advance
Pawel

It is my experience that Government likes VHDL while the commercial
industry likes Verilog. Given the choice I would probably always use
Verilog. You can go to opencores.org and see what they have to offer -
this may help you make your choice.

-Derek

 

[raul]

In my case Verilog has been the language that my employers or customers
use so it is "backward compatibility" that dictated my use of verilog.
VHDL does look verbose from examples that I have seen...

RAUL

 

[y_p_w]

Pawel wrote:

Hello All

Can anybody give me link to the discussion on
advantages and disadvantages on using VHDL and
Verilog?
The selection should be constrained only to the
digital hardware.

I prefer Verilog. More precise and defined. You generally don't
need to worry about packages or assorted things that need to be
plugged in. Certainly VHDL is flexible, but I find that all the
built-in stuff into Verilog is good enough. If I'm going to start
a design from scratch, It'll be in Verilog.

About the only thing that I prefer about VHDL is the possibility
of "types" for state encoding. You don't have to explicitly
define state bit encodings, and there less room for error when
expanding the number of states. The drawback was when I had to
debug synthesized netlists, it was difficult to correlate the
state bits with their definitions.

That being said, I know how to code and read both. I use mixed-
language simulators at work, and the work I do typically includes
VHDL and Verilog in the same design. As a strange aside, I once
used a synthesizable core for a certain external interface. The
core itself was written in VHDL. The behavioral bus functional
model used to verify the design was written in Verilog.