VHDL+verilog design, strange simulation issue

[Akshaye]

Hi,

I had this wierd issue with vhdl-verilog co-simulation.

I have a net which is driven in VHDL and is used as an input to 2
verilog designs which are instantiated in this VHDL block.

|-----
|----->|verilog A
| |-----
VHDL ----|
| |-----
|----->|verilog B
|-----

The net is directly used on ports on the verilog modules. Now if i
assign this internal net in "verilog A" module via PLI, a strange
thing happens in the simulator. The net inside verilog A is assigned
this value, the net inside verilog B is assigned this value(wierd?)
but the top level net in VHDL does not get this value!

I have no issue with the VHDL net not getting the assigned
value(because its direction is opposite), but what complicates
debugging is that it is assigned in verilog B.

Is this some optimisation in the simulator which moves this net node
from VHDL to verilog possibly to reduce VHDL to verilog boundary
signals? Can somebody provide an expaination for this? is it simulator
dependent?

Thanks in advance.

 

[Srinivasan Venkataramanan]

Hi Akshaye,
Try this:
1. Try assigning the value through your Simulator's TCL (or its own
interface) interface, in NC, I could do

force vhdl_top.log_a.net = 0;

and see if vlog_b instance also gets this value.

Show us the piece of PLI code that you use to assign, I guess traversing
through VHDL is not allowed with pure PLI, how are you doing this?
Which simulator are you using?

HTH,
Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer, Intel Bangalore, India
Co-Author of: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition,
2004 isbn 0-9705394-6-0, Ben Cohen, Srinivasan & Ajeetha

http://www.noveldv.com
I don't speak for Intel

"Akshaye" <sam22277@yahoo.com> wrote in message
news:913cdaa6.0402060819.53fff796@posting.google.com...

Hi,

I had this wierd issue with vhdl-verilog co-simulation.

I have a net which is driven in VHDL and is used as an input to 2
verilog designs which are instantiated in this VHDL block.

|-----
|----->|verilog A
| |-----
VHDL ----|
| |-----
|----->|verilog B
|-----

The net is directly used on ports on the verilog modules. Now if i
assign this internal net in "verilog A" module via PLI, a strange
thing happens in the simulator. The net inside verilog A is assigned
this value, the net inside verilog B is assigned this value(wierd?)
but the top level net in VHDL does not get this value!

I have no issue with the VHDL net not getting the assigned
value(because its direction is opposite), but what complicates
debugging is that it is assigned in verilog B.

Is this some optimisation in the simulator which moves this net node
from VHDL to verilog possibly to reduce VHDL to verilog boundary
signals? Can somebody provide an expaination for this? is it simulator
dependent?

Thanks in advance.