VHDL to Verilog (help)

  • Thread starter Choonho Root PLlab.
  • Start date
C

Choonho Root PLlab.

Guest
I am newbie in Verilog and VHDL.

I have to exchange VHDL example to Verilog

------------VHDL CODE-----------------
PROCESS(NPX_PWE)
BEGIN
IF NPX_PWE'EVENT AND NPX_PWE='1' THEN

....
END IF;
END PROCESS;

-----------------------------

can anyone translate this code to Verilog code
 
On 23 Feb 2005 15:51:08 +0900, root@opal.kaist.ac.kr (Choonho Root
PLlab.) wrote:

I am newbie in Verilog and VHDL.

I have to exchange VHDL example to Verilog

------------VHDL CODE-----------------
PROCESS(NPX_PWE)
BEGIN
IF NPX_PWE'EVENT AND NPX_PWE='1' THEN

...
END IF;
END PROCESS;

-----------------------------

can anyone translate this code to Verilog code
Yes!

always @(posedge(NPX_PWE))
begin
...
end


Note that your VHDL could be written as:

if rising_edge(NPX_PWE) then

instead of

IF NPX_PWE'EVENT AND NPX_PWE='1' THEN


Regards,
Allan
 

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