C
Choonho Root PLlab.
Guest
I am newbie in Verilog and VHDL.
I have to exchange VHDL example to Verilog
------------VHDL CODE-----------------
PROCESS(NPX_PWE)
BEGIN
IF NPX_PWE'EVENT AND NPX_PWE='1' THEN
....
END IF;
END PROCESS;
-----------------------------
can anyone translate this code to Verilog code
I have to exchange VHDL example to Verilog
------------VHDL CODE-----------------
PROCESS(NPX_PWE)
BEGIN
IF NPX_PWE'EVENT AND NPX_PWE='1' THEN
....
END IF;
END PROCESS;
-----------------------------
can anyone translate this code to Verilog code