VHDL to Verilog converter

[Amir]

Hi all,

do you know any good program that converts VHDL to Verilog ?!

thanks in advance
-Amir

 

[HT-Lab]

"Amir" <sting.t2@gmail.com> wrote in message
news:1188975738.872743.148600@w3g2000hsg.googlegroups.com...

Hi all,

do you know any good program that converts VHDL to Verilog ?!

Personally I wouldn't go down this route but you can try XHDL
(http://www.ids4eda.com/xhdl.htm), you might have to do some manual editing
before converting. Why are you trying to do this?

Hans
www.ht-lab.com

thanks in advance
-Amir

 

[Amir]

thanks,

well I am working on a Verilog Project, and received from my partner a
module in VHDL, I want to integrate it to the Project.

by the way , found a free one , I don't know if you know it
http://www.ocean-logic.com/downloads.htm

-Amir

 

[Kim Enkovaara]

Amir wrote:

well I am working on a Verilog Project, and received from my partner a
module in VHDL, I want to integrate it to the Project.

Just intergate the VHDL code directly inside the verilog. All the real
tools nowadays support mixed mode functionality (simulation, synthesis etc.)

--Kim

 

[HT-Lab]

"Amir" <sting.t2@gmail.com> wrote in message
news:1188982229.702139.141850@22g2000hsm.googlegroups.com...

thanks,

well I am working on a Verilog Project, and received from my partner a
module in VHDL, I want to integrate it to the Project.

by the way , found a free one , I don't know if you know it
http://www.ocean-logic.com/downloads.htm

-Amir

Hi Amir,

I fully agree with Kim in that you can save yourself a lot of hassle by just
adding the VHDL core to your project. If you don't have access to a dual
language license (as is required by e.g. Modelsim) then perhaps you can
synthesize the VHDL design and write out a netlist in Verilog. I won't be
quick to simulate but it might enable you to test your whole design.

Hans
www.ht-lab.com

 

[Amir]

On Sep 5, 2:15 pm, "HT-Lab" <han...@ht-lab.com> wrote:

"Amir" <sting...@gmail.com> wrote in message

news:1188982229.702139.141850@22g2000hsm.googlegroups.com...

thanks,

well I am working on a Verilog Project, and received from my partner a
module in VHDL, I want to integrate it to the Project.
Hi Hans and Kim,

The thing is I don't know VHDL , and if there is a bug in the VHDL
code I believe I won't find it easly.
and the free converter (that I linked in my previous message 'ocean-
logic') code is really bad :-\
but what Hans recommended program, I heard it's a good one but it's
not for free.

-Amir

by the way , found a free one , I don't know if you know it
http://www.ocean-logic.com/downloads.htm

-Amir

Hi Amir,

I fully agree with Kim in that you can save yourself a lot of hassle by just
adding the VHDL core to your project. If you don't have access to a dual
language license (as is required by e.g. Modelsim) then perhaps you can
synthesize the VHDL design and write out a netlist in Verilog. I won't be
quick to simulate but it might enable you to test your whole design.

Hanswww.ht-lab.com

 

[Kim Enkovaara]

Amir wrote:

The thing is I don't know VHDL , and if there is a bug in the VHDL
code I believe I won't find it easly.
and the free converter (that I linked in my previous message 'ocean-
logic') code is really bad :-\

My guess is that the VHDL->verilog converters all do quite bad code.
It should not take more than few days to learn basics of VHDL, if
you know how to code RTL in verilog.

If the code is very simple VHDL the differences are small to Verilog.
And if the VHDL uses heavily records and other fancy stuff, the
converted result will be really hard to read and fix.

--Kim