vhdl to blif

[Fabio]

Hi!
I'm an italian student and I need to translate a vhdl source into blif (to
check with vis) for my thesis.
So I'm looking for a vhdl to blif translator (for linux). Can we help me?
Thanks in advance,
Fabio

 

[Just an Illusion]

Hi Fabio,

Look in Alliance project (www-asim.lip6.fr/recherche/alliance) and vis
(http://vlsi.colorado.edu/~vis) page.

But trust me, the most simple way to do it, is translating your design
into Verilog, or as netlist (better), if you have a synthesizer for any
libraries try to use gtech (the cells modelization for this library is
very easy). I have done it with Leonard Spectrum with compilation for
Max9000 library, and modelize in blif all cells from library (I need
modified my cells library if you want it, because it embedded some
custom variable, that you couldn't handle)

From a verilog file, search for the tool v2blif, this is a verilog to
blif translator. Not too bad.

Bye,
JaI

Fabio wrote:

Hi!
I'm an italian student and I need to translate a vhdl source into blif (to
check with vis) for my thesis.
So I'm looking for a vhdl to blif translator (for linux). Can we help me?
Thanks in advance,
Fabio