VHDL-Testbench-Simulation in QuartusII

[ALuPin]

Hi @ all,

how can I simulate a testbench written in VHDL in QuartusII 3.0
software?

Do I have to save it as a .vhd file or what kind of file is needed
to simulate with Altera-Modelsim?

Under SETTINGS --> EDA TOOL SETTINGS --> SIMULATION I choose
ModelSim-Altera
Under SETTINGS --> EDA TOOL SETTINGS ---> SIMULATION
--> ADVANCED
there can be chosen "Test Bench Mode". But when I want to select
the Test Bench File there are only .vht files?
How can I save a .vhd file as a .vht file?

Thank you very much

Kind regards
A.Lapa

 

[Mike Treseler]

ALuPin wrote:

how can I simulate a testbench written in VHDL in QuartusII 3.0
software?

Use modelsim.

related thread:

http://groups.google.com/groups?q=ranjith+oe_demo

-- Mike Treseler

 

[Subroto Datta]

http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht.
html

- Subroto Datta
Altera Corp.




A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
with a .vht extension.



"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0312050619.24a357e6@posting.google.com...

Hi @ all,

how can I simulate a testbench written in VHDL in QuartusII 3.0
software?

Do I have to save it as a .vhd file or what kind of file is needed
to simulate with Altera-Modelsim?

Under SETTINGS --> EDA TOOL SETTINGS --> SIMULATION I choose
ModelSim-Altera
Under SETTINGS --> EDA TOOL SETTINGS ---> SIMULATION
--> ADVANCED
there can be chosen "Test Bench Mode". But when I want to select
the Test Bench File there are only .vht files?
How can I save a .vhd file as a .vht file?

Thank you very much

Kind regards
A.Lapa

 

[ALuPin]

"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...

http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht.
html

- Subroto Datta
Altera Corp.




A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
with a .vht extension.

Hi,

yes I read about it in the handbook, but HOW can I save a .vhd file as
a .vht file?

When I write a testbench file I can only save it as .vhd ! ?

Thank you.

 

[Subroto Datta]

In this case rename your vhd file which contains the testbench to the .vht
extension using the Windows Explorer or DOS prompt.

- Subroto


"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0312072313.3cd8ecc@posting.google.com...

"Subroto Datta" <sdatta@altera.com> wrote in message
news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...

http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht.
html

- Subroto Datta
Altera Corp.




A VHDL Test Bench File is the same as a standard VHDL test bench file,
saved
with a .vht extension.



Hi,

yes I read about it in the handbook, but HOW can I save a .vhd file as
a .vht file?

When I write a testbench file I can only save it as .vhd ! ?

Thank you.

 

[ALuPin]

In this case rename your vhd file which contains the testbench to the .vht
extension using the Windows Explorer or DOS prompt.

- Subroto

Hi,

are the following settings right ?


Settings --> EDA Tool Settings --> Advanced VHDL Simulation Options

--> Test Bench Mode: Test Bench File: ...tb_reservoir_positions.vht
Test Bench entity name: ...tb_reservoir_positions.vht



reservoir_positions.vhd is the module to be simulated (and therefore
it is instantiated in the testbench tb_reservoir_positions.vht)

There seems to be some problem with it because after compiling I get the
following error messages:

- Error: Compilation of design file Reservoir_positions.vho was NOT successful
- ModelSim couldn't execute "vcom": no such file or directory
- Error: Compilation of test bench file ... tb_reservoir_positions.vht was NOT
successful
- Error: Simulation of design tb_reservoir_positions.vht was NOT successful

Thanks
Andre V.

 

[Andy Peters]

"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...

A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
with a .vht extension.

Why do vendors insist on using non-standard extensions for VHDL (and
Verilog) source files? (Altera's not the only one.)

Emacs, for example, knows that a .vhd file is VHDL and a .v file is
Verilog. It doesn't know about a .vht file, unless I go and tell it.
ModelSim recognizes .vhd and .v files but doesn't know from .vht
files.

The solution, of course, is to rename the files created by the tools.

FWIW, I've adopted a simple notation to indicate that a file is a test
bench: given a module foo.vhd, its test bench is called foo_tb.vhd.

--a

 

[Mike Treseler]

ALuPin wrote:

- ModelSim couldn't execute "vcom": no such file or directory
- Error: Compilation of test bench file ... tb_reservoir_positions.vht was NOT
successful
- Error: Simulation of design tb_reservoir_positions.vht was NOT successful

Consider vcom and vsim from the command line, not from Quartus.

-- Mike Treseler

 

[ALuPin]

Consider vcom and vsim from the command line, not from Quartus.

-- Mike Treseler

Hi Mike,

ok let's consider vcom and vsim from the command line ...
what does I learn from it? )

Thanks.

Kind regards

Andre V.

 

[Martin Thompson]

Bassman59a@yahoo.com (Andy Peters) writes:

"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...


A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
with a .vht extension.


Why do vendors insist on using non-standard extensions for VHDL (and
Verilog) source files? (Altera's not the only one.)

Emacs, for example, knows that a .vhd file is VHDL and a .v file is
Verilog. It doesn't know about a .vht file, unless I go and tell it.
ModelSim recognizes .vhd and .v files but doesn't know from .vht
files.

The solution, of course, is to rename the files created by the tools.

For emacs , the solution is to stick this sort of thing in your .emacs
file:
(setq auto-mode-alist (append '(("\\.vht?$" . vhdl-mode)) auto-mode-alist))

Tweak the "vht" to suit...

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Mike Treseler]

ALuPin wrote:

Hi Mike,

ok let's consider vcom and vsim from the command line ...
what does I learn from it? )

Well, let's try it and see:

61 steptoe Mon Dec 15 /usr0/tres/marge/fpga/fr/vhdl > vcom

Model Technology ModelSim SE vcom 5.7c Compiler 2003.03 Mar 13 2003

Usage: vcom [options] files

Options:
-help Print this message
-version Print the version of the compiler
-work <path> Specify library WORK
-87 Disable support for 1076-1993
-93 Enable support for 1076-1993
-check_synthesis Check for compliance to some synthesis rules
-debugVA Print VITAL cell optimization information
-defercheck Defer all compile-time range checking on constant index and
slice expressions until run time
-explicit Resolve resolution conflicts in favor of explicit functions
+acc[=<spec>][+<entity>[(<architecture&gt]]
Enable access to objects indicated by <spec> when
optimizing with -O4 or -O5, for processes merged
under certain conditions, where <spec> is the
character:
v (variables, constants, and aliases).
Optionally, enable access only for specific entities
and their associated architectures.
-f <path> Specify file containing more command line arguments
-gen_xml <entity> <output>
Output (into a file) the interface definition of the
specified entity in XML format.
-force_refresh Force Refresh library image from .dat file(s) even if
there are errors
-ignoredefaultbinding
Do not generate a default binding during compilation
-ignorevitalerrors Ignore VITAL compliance errors
-just eapbc Compile only selected design unit kinds
(e=entity, a=arch, p=package, b=body, c=config)
-line <lineNum> Specify starting line number
-lint Perform lint-style checks
-no1164 Disable optimization for the std_logic_1164 package
-noaccel <pname> Disable optimization for the specified package
-nocasestaticerror Suppress case static warnings
-nocheck Disable run-time range and index checks
-nodebug Do not put symbolic debugging information into library
-noindexcheck Disable run-time index checks
-nologo Disable startup banner
-norangecheck Disable run-time range checks
-novital Disable all VITAL optimizations
-novitalcheck Disable VITAL Level 1 compliance checking and optimizations
-nowarn <number> Do not flag warnings for the warning number specified
-O0 Disable optimizations
-O1 Enable some optimizations
-O4 Enable most optimizations (default)
-O5 Enable additional compiler optimizations
-pedanticerrors Enforce strict static checks
-performdefaultbinding
Enable default binding when it has been disabled with the
RequireConfigForAllDefaultBinding modelsim.ini variable
-quiet Disable 'Loading' messages
-refresh Refresh library image from .dat file(s)
-s Do not load package standard
-skip eapbc Compile all but selected design unit kinds
(e=entity, a=arch, p=package, b=body, c=config)
-source Print the source line with error messages
62 steptoe Tue Dec 16 /usr0/tres/marge/fpga/fr/vhdl >