VHDL Testbench representation

[JSreeniv]

Hi all,

Could anyone give the response on this..

I am writing VHDL testbench for my code. And i am stuck at the writing
testbench piece...here is the description

WAIT FOR 5 us

Repeat READ(Address) for every 1 us

Where the READ process should be repeat for 5 times..
Can anyone give me the ideas to write the code for this piece of
description

Sreeni

 

[KJ]

On Aug 16, 2:13 am, JSreeniv <sreenivas.jyo...@gmail.com> wrote:

Hi all,

Could anyone give the response on this..

I am writing VHDL testbench for my code. And i am stuck at the writing
testbench piece...here is the description

WAIT FOR 5 us

Repeat READ(Address) for every 1 us

Where the READ process should be repeat for 5 times..
Can anyone give me the ideas to write the code for this piece of
description

The 'read process' should probably be a 'read procedure' that gets
invoked within a process within your testbench. Something like the
following...needs more work, but it's a sketch of the overall
structure

entity testbench is
end testbench;

architecture RTL of testbench is
signal Sim_In_Progress: Boolean;

begin
process main
procedure read(Address: integer) is
begin
-- fill in your procedure code here
end procedure read;
begin
wait for 5 us;
while Sim_In_Progress loop
read(Address => 10); -- Example
wait for 1 us;
end loop;
end process;

Sim_In_Progress <= '1', '0' after 10 ms; -- However you want it to
be controlled
end RTL;

Kevin Jennings

 

[KJ]

On Aug 16, 2:25 pm, KJ <kkjenni...@sbcglobal.net> wrote:

On Aug 16, 2:13 am, JSreeniv <sreenivas.jyo...@gmail.com> wrote:

Just noticed that you wanted the reading to happen only 5 times. So
instead of this...

while Sim_In_Progress loop
read(Address => 10); -- Example
wait for 1 us;
end loop;

You would want to have this...
for i in 1 to 5 loop
read(Address => 10); -- Example
wait for 1 us;
end loop;

Kevin Jennings