VHDL Test Bench + Help

[SneakerNet]

Hello all
I need some introductory help with writing test bench cases for my VHDL
code.
I have written a lot of VHDL code, however I have always tested this using
waveform simulation and then finally testing it on the product. I wish to go
one step further by learning how to write test cases.

Can someone give me a starting point to this pls? Is there a website that
explains how to write test bench code? I am using Altera FPGAs and thus
using Quartus II to write my VHDL code at present.

Pls advice.

Thank you

 

[fpga kid]

A great vhdl online reference
http://www.vhdl-online.de/~vhdl/

 

[Mohammed khader]

HI,

If you have not wrriten any test bench yet .... then Start writing it
for combinaitonal logic first ... ( Like nand gate, mux, decoder,
Priority Encoder)... Then go for sequential logic ( Like Simple Fsm s
for sequence detector and so on )..

You need a good guide or a good book to start with. Here are few web
site where you can find some good stuff..

http://www.acc-eda.com/vhdlref/refguide/language_overview/test_benches/test_benches.htm

http://members.aol.com/SGalaxyPub/useful_links_vhdl.htm
Regards,
Mohammed A Khader.