VHDL / SystemC Cosimulation problem

M

manu

Guest
Hi,
I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
design.
All my synthesisable modules are written in VHDL and all my test benches
are written in SystemC since it offers very convenient features to build
complex test scenarios.
Until Now, it was OK since all my VHDL modules had "trivial" data types
on their ports (eg. std_logic and std_logic_vector). So the generation
of SystemC wrappers for my HDL modules was very easy thank to
"scgenmod" command.
Now, I want to use a custom data type like the following one :

package mytypes is
type my_custom_type_t is record
my_flag : std_logic;
my_bus : std_logic_vector(WIDTH-1 downto 0);
more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
end record;
end package;

and for my entity :

entity mydesign_top is
port
(
custom_input : in my_custom_type_t;

...All my other stuff...
);
end mydesign_top;

The problem is I don't know any "smart" way to bind a SytemC type to my
custom VHDL type. The only workaround I found for the moment is to
encapsulate my VHDL module into a VHDL wrapper in which I perform a
breakout of my custom type :

entity mydesign_top_wrap is
port
(
--begin custom_input breakout
custom_input_flag : std_logic;
custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
--end custom_input breakout

...All my other stuff...
);
end mydesign_top_wrap;

But I don't like this solution because it is very hard to maintain my
whole source code when I modify the definition of my_custom_type_t.
Idealy, I would like to have only two file to modify : the VHDL package
and a corresponding C++ header in which would be defined the type mapping.
Does anyone know how to do this or any clean workaround ?
thanks for your help !

Manu
 
manu wrote:

All my synthesisable modules are written in VHDL and all my test benches
are written in SystemC since it offers very convenient features to build
complex test scenarios.
....
The problem is I don't know any "smart" way to bind a SytemC type to my
custom VHDL type. The only workaround I found for the moment is to
encapsulate my VHDL module into a VHDL wrapper in which I perform a
breakout of my custom type :
Click to expand...
I prefer to make all my top ports
std_logic_vectors and
std_ulogic bits because these types
are support by all tools and all designers.

I declare my_custom_types_t inside
the top architecture. Most of the real wide,
interesting structures are inside anyway.

-- Mike Treseler
 
Hi Manu,

Interesting question. I suspect that this is not possible given the
restriction of only supporting locally static subtypes and arrays. However,
I would suggest you pass this on to Mentor support and see what they come
back with. You might also want to try the OSCI SystemC newsgroup. If you
find a solution please post it here and/or send me an email since I am also
interested in this.

Hans
www.ht-lab.com




"manu" <manuel.pezzin@free.fr> wrote in message
news:44342e94$0$27279$626a54ce@news.free.fr...
Hi,
I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
design.
All my synthesisable modules are written in VHDL and all my test benches
are written in SystemC since it offers very convenient features to build
complex test scenarios.
Until Now, it was OK since all my VHDL modules had "trivial" data types on
their ports (eg. std_logic and std_logic_vector). So the generation of
SystemC wrappers for my HDL modules was very easy thank to "scgenmod"
command.
Now, I want to use a custom data type like the following one :

package mytypes is
type my_custom_type_t is record
my_flag : std_logic;
my_bus : std_logic_vector(WIDTH-1 downto 0);
more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
end record;
end package;

and for my entity :

entity mydesign_top is
port
(
custom_input : in my_custom_type_t;

...All my other stuff...
);
end mydesign_top;

The problem is I don't know any "smart" way to bind a SytemC type to my
custom VHDL type. The only workaround I found for the moment is to
encapsulate my VHDL module into a VHDL wrapper in which I perform a
breakout of my custom type :

entity mydesign_top_wrap is
port
(
--begin custom_input breakout
custom_input_flag : std_logic;
custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
--end custom_input breakout

...All my other stuff...
);
end mydesign_top_wrap;

But I don't like this solution because it is very hard to maintain my
whole source code when I modify the definition of my_custom_type_t.
Idealy, I would like to have only two file to modify : the VHDL package
and a corresponding C++ header in which would be defined the type mapping.
Does anyone know how to do this or any clean workaround ?
thanks for your help !

Manu
Click to expand...
 
Hi Manu!

I asked my fellow here and they said "hummm... you'll have to wrap it"!

anyway, maybe the following functions may help:
mti_GetNumRecordElements
mti_GetSignalSubelements
and so on...

the doc is on <yourlocalmodeltechinstall>/docs/se_html/se_fli/

and also an example is
<modeltech>/examples/vhdl/foreign/example_four/foreignsp.vhd
(this one is pure C)

HTH and that we'll have a beer together one of these days!
Stephane

manu wrote:
Hi,
I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
design.
All my synthesisable modules are written in VHDL and all my test benches
are written in SystemC since it offers very convenient features to build
complex test scenarios.
Until Now, it was OK since all my VHDL modules had "trivial" data types
on their ports (eg. std_logic and std_logic_vector). So the generation
of SystemC wrappers for my HDL modules was very easy thank to
"scgenmod" command.
Now, I want to use a custom data type like the following one :

package mytypes is
type my_custom_type_t is record
my_flag : std_logic;
my_bus : std_logic_vector(WIDTH-1 downto 0);
more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
end record;
end package;

and for my entity :

entity mydesign_top is
port
(
custom_input : in my_custom_type_t;

...All my other stuff...
);
end mydesign_top;

The problem is I don't know any "smart" way to bind a SytemC type to my
custom VHDL type. The only workaround I found for the moment is to
encapsulate my VHDL module into a VHDL wrapper in which I perform a
breakout of my custom type :

entity mydesign_top_wrap is
port
(
--begin custom_input breakout
custom_input_flag : std_logic;
custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
--end custom_input breakout

...All my other stuff...
);
end mydesign_top_wrap;

But I don't like this solution because it is very hard to maintain my
whole source code when I modify the definition of my_custom_type_t.
Idealy, I would like to have only two file to modify : the VHDL package
and a corresponding C++ header in which would be defined the type mapping.
Does anyone know how to do this or any clean workaround ?
thanks for your help !

Manu
Click to expand...
 
I might be wrong but I don't think the FLI interface is going to help him.
The VHDL/SystemC interface of Modelsim is very easy, adding an FLI layer
will make it far too complex and less portable IMHO. Perhaps the wrapper is
the only solution.....?

Hans
www.ht-lab.com


"Stephane" <stephane@nospam.fr> wrote in message
news:e13f8h$93c$1@ellebore.extra.cea.fr...
Hi Manu!

I asked my fellow here and they said "hummm... you'll have to wrap it"!

anyway, maybe the following functions may help:
mti_GetNumRecordElements
mti_GetSignalSubelements
and so on...

the doc is on <yourlocalmodeltechinstall>/docs/se_html/se_fli/

and also an example is
modeltech>/examples/vhdl/foreign/example_four/foreignsp.vhd
(this one is pure C)

HTH and that we'll have a beer together one of these days!
Stephane

manu wrote:
Hi,
I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
design.
All my synthesisable modules are written in VHDL and all my test benches
are written in SystemC since it offers very convenient features to build
complex test scenarios.
Until Now, it was OK since all my VHDL modules had "trivial" data types
on their ports (eg. std_logic and std_logic_vector). So the generation of
SystemC wrappers for my HDL modules was very easy thank to "scgenmod"
command.
Now, I want to use a custom data type like the following one :

package mytypes is
type my_custom_type_t is record
my_flag : std_logic;
my_bus : std_logic_vector(WIDTH-1 downto 0);
more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
end record;
end package;

and for my entity :

entity mydesign_top is
port
(
custom_input : in my_custom_type_t;

...All my other stuff...
);
end mydesign_top;

The problem is I don't know any "smart" way to bind a SytemC type to my
custom VHDL type. The only workaround I found for the moment is to
encapsulate my VHDL module into a VHDL wrapper in which I perform a
breakout of my custom type :

entity mydesign_top_wrap is
port
(
--begin custom_input breakout
custom_input_flag : std_logic;
custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
--end custom_input breakout

...All my other stuff...
);
end mydesign_top_wrap;

But I don't like this solution because it is very hard to maintain my
whole source code when I modify the definition of my_custom_type_t.
Idealy, I would like to have only two file to modify : the VHDL package
and a corresponding C++ header in which would be defined the type
mapping.
Does anyone know how to do this or any clean workaround ?
thanks for your help !

Manu
Click to expand...
 
Hi Stephane,
I agree with Hans. Actually I really don't like the FLI and if I had to
choose, I prefer the initial VHDL wrapper solution.
I will post this topic on SystemC mailing list too and get in touch with
Mentor support.
Answer(s) in the next post (I hope...).

Manu

PS : And for the beer, I hope too ! ;-)

Hans a écrit :
I might be wrong but I don't think the FLI interface is going to help him.
The VHDL/SystemC interface of Modelsim is very easy, adding an FLI layer
will make it far too complex and less portable IMHO. Perhaps the wrapper is
the only solution.....?

Hans
www.ht-lab.com


"Stephane" <stephane@nospam.fr> wrote in message
news:e13f8h$93c$1@ellebore.extra.cea.fr...

Hi Manu!

I asked my fellow here and they said "hummm... you'll have to wrap it"!

anyway, maybe the following functions may help:
mti_GetNumRecordElements
mti_GetSignalSubelements
and so on...

the doc is on <yourlocalmodeltechinstall>/docs/se_html/se_fli/

and also an example is
modeltech>/examples/vhdl/foreign/example_four/foreignsp.vhd
(this one is pure C)

HTH and that we'll have a beer together one of these days!
Stephane

manu wrote:

Hi,
I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
design.
All my synthesisable modules are written in VHDL and all my test benches
are written in SystemC since it offers very convenient features to build
complex test scenarios.
Until Now, it was OK since all my VHDL modules had "trivial" data types
on their ports (eg. std_logic and std_logic_vector). So the generation of
SystemC wrappers for my HDL modules was very easy thank to "scgenmod"
command.
Now, I want to use a custom data type like the following one :

package mytypes is
type my_custom_type_t is record
my_flag : std_logic;
my_bus : std_logic_vector(WIDTH-1 downto 0);
more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
end record;
end package;

and for my entity :

entity mydesign_top is
port
(
custom_input : in my_custom_type_t;

...All my other stuff...
);
end mydesign_top;

The problem is I don't know any "smart" way to bind a SytemC type to my
custom VHDL type. The only workaround I found for the moment is to
encapsulate my VHDL module into a VHDL wrapper in which I perform a
breakout of my custom type :

entity mydesign_top_wrap is
port
(
--begin custom_input breakout
custom_input_flag : std_logic;
custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
...
--end custom_input breakout

...All my other stuff...
);
end mydesign_top_wrap;

But I don't like this solution because it is very hard to maintain my
whole source code when I modify the definition of my_custom_type_t.
Idealy, I would like to have only two file to modify : the VHDL package
and a corresponding C++ header in which would be defined the type
mapping.
Does anyone know how to do this or any clean workaround ?
thanks for your help !

Manu
Click to expand...
 
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