J
jesse lackey
Guest
I'm using xilinx ISE 9.1.
On the below, I get:
ERROR:HDLParsers:164 - "F:/dev/len/4chan/vhdl_learning/try1.vhd" Line
243. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR
on the line:
" if (which samp_out = 4) then "
and I'm at my wit's end. I'm new to VHDL so it is probably something
I'm doing. But I've spent an hour doing creative commenting-out (this
is part of a larger process) and getting nowhere and now it is a
showstopper.
my apologies for the poor formatting.
any advice greatly appreciated.
Thanks in advance.
Jesse
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity multiplexed_output is
Port (
m_clock : in STD_LOGIC; -- master clock
global_reset : in STD_LOGIC;
spdif_A_lr : out STD_LOGIC -- l/r signal (1=left)
);
end multiplexed_output;
architecture Behavioral of multiplexed_output is
begin
process (m_clock,global_reset)
variable spdif_lr_counter : integer range 0 to 1000;
variable spdif_lr_phase : STD_LOGIC;
variable spdif_lr_counter_top : integer range 0 to 1000;
variable which_samp_out : integer range 0 to 1000;
begin
if (global_reset = '1') then
spdif_lr_counter := 0;
spdif_lr_phase := '0';
which_samp_out := 0;
spdif_lr_counter_top := 128;
elsif (m_clock'EVENT and m_clock='1') then -- rising edge
spdif_lr_counter := spdif_lr_counter +1;
if (spdif_lr_counter = spdif_lr_counter_top) then -- time to flip l/r
to spdif transmitters
spdif_lr_counter := 0;
spdif_lr_phase := not spdif_lr_phase;
which_samp_out := which_samp_out +1;
if (which samp_out = 4) then
which_samp_out := 0;
end if;
end if;
spdif_A_lr <= spdif_lr_phase;
end if;
end process;
end Behavioral;
On the below, I get:
ERROR:HDLParsers:164 - "F:/dev/len/4chan/vhdl_learning/try1.vhd" Line
243. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR
on the line:
" if (which samp_out = 4) then "
and I'm at my wit's end. I'm new to VHDL so it is probably something
I'm doing. But I've spent an hour doing creative commenting-out (this
is part of a larger process) and getting nowhere and now it is a
showstopper.
my apologies for the poor formatting.
any advice greatly appreciated.
Thanks in advance.
Jesse
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity multiplexed_output is
Port (
m_clock : in STD_LOGIC; -- master clock
global_reset : in STD_LOGIC;
spdif_A_lr : out STD_LOGIC -- l/r signal (1=left)
);
end multiplexed_output;
architecture Behavioral of multiplexed_output is
begin
process (m_clock,global_reset)
variable spdif_lr_counter : integer range 0 to 1000;
variable spdif_lr_phase : STD_LOGIC;
variable spdif_lr_counter_top : integer range 0 to 1000;
variable which_samp_out : integer range 0 to 1000;
begin
if (global_reset = '1') then
spdif_lr_counter := 0;
spdif_lr_phase := '0';
which_samp_out := 0;
spdif_lr_counter_top := 128;
elsif (m_clock'EVENT and m_clock='1') then -- rising edge
spdif_lr_counter := spdif_lr_counter +1;
if (spdif_lr_counter = spdif_lr_counter_top) then -- time to flip l/r
to spdif transmitters
spdif_lr_counter := 0;
spdif_lr_phase := not spdif_lr_phase;
which_samp_out := which_samp_out +1;
if (which samp_out = 4) then
which_samp_out := 0;
end if;
end if;
spdif_A_lr <= spdif_lr_phase;
end if;
end process;
end Behavioral;