Guest
Is there a way to write a VHDL synchronizer function that could be called from a section of sequential code as:
if sync(clock, a) = '1' then...
where "a" is a signal from another clock domain and "clock" is the clock in the present domain?
I've tried
function sync(clock, in: std_logic) return std_logic is
variable med, result: std_logic;
begin
if clock'event and clock = '1' then
med := input;
result := med;
end if;
return result;
end sync;
The result in the Xilinx simulator is syntactically accepted but is always undefined, no matter how many variations of the above I tried.
Is there a technique which preserves the convenience of my approach but works?
Geno
if sync(clock, a) = '1' then...
where "a" is a signal from another clock domain and "clock" is the clock in the present domain?
I've tried
function sync(clock, in: std_logic) return std_logic is
variable med, result: std_logic;
begin
if clock'event and clock = '1' then
med := input;
result := med;
end if;
return result;
end sync;
The result in the Xilinx simulator is syntactically accepted but is always undefined, no matter how many variations of the above I tried.
Is there a technique which preserves the convenience of my approach but works?
Geno