VHDL Style

[Mounard le Fuogueux]

Hey!

I've been doing VHDL for a while and am stuck in a stylistic rut - using
purely behavioural constructs with very spare and terse logic
(minimalist) -

I
- avoid variables unless really need them in favor of signals
- avoid sm's unless really need them in favor of proceses
- avoid proceedures unless really need them

In other words I presently favor high parallelism over sequentialism and
avoid software engineering principles as beaurocratic and obfuscatory
(Imagine trying to read a book in which the meaning if every word and
phrase is located somewhere else - highly beaurocratic and not helpfull
(please - this is not meant to start a discussion over the merits of SE)).

What I'm after is links or references to alternate vhdl styles, that
display a certain internal consistemcy of style that has particular
power in certain contexts and benefits from a consistency of style (and
thus readibility and also templateability) in all other contexts.

I vauguely remember M. Treseler used to try to evangelise a particular
syle but can't find that any more. That sort of thing.

I'm into a change of VHDL lifestyle in my VHDL midlife crisis.

Thanks

 

[Mike Treseler]

Mounard le Fuogueux wrote:

I vauguely remember M. Treseler used to try to evangelise a particular
syle but can't find that any more. That sort of thing.

I'm into a change of VHDL lifestyle in my VHDL midlife crisis.

Variables, functions and procedures may be
used for a sequential description of parallel
hardware that works just as well as the
as conventional descriptions for FPGA targets.
Use the RTL viewer to check the synthesis view.

Some examples:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[Andy]

I agree with a lot of the principles of what Mike uses.

I generally favor variables over signals because they behave truly
sequentially in sequential contexts (processes). Signals do not behave
truly sequentially (update pending wait). So, vhdl coded with
variables reads and behaves like SW, not some strange hybrid.

I generally prefer relatively few processes per architecture, based on
relative isolation of functionality, and/or need to share information
(variables are not visible between different processes). Isolation can
also be handled within blocks or subprograms within a single process.

I sometimes use procedures/functions when a chunk of a process is used
repeatedly, or is more easily understood when given and called with a
descriptive name.

Unless you are talking about implicit state machines (using multiple
wait statements in a process), I don't understand your preference for
processes over state machines. Even with implicit state machines, they
are generally less flexible than ordinary, explicit state machines.

I use clocked processes unless I require a combinatorial logic path
from input to output in the entity (rarely). Variables make
everything else easier to handle from a clocked process.

I use integer subtypes and booleans instead of std_logic_vector and
std_logic as much as possible. Easier to handle arithmetic, and they
simulate MUCH faster.

Andy

On Mar 20, 7:52 am, Mounard le Fuogueux
<BlinkingCur...@NonEventHorizon.com> wrote:

Hey!

I've been doing VHDL for a while and am stuck in a stylistic rut - using
purely behavioural constructs with very spare and terse logic
(minimalist) -

I
- avoid variables unless really need them in favor of signals
- avoid sm's unless really need them in favor of proceses
- avoid proceedures unless really need them

In other words I presently favor high parallelism over sequentialism and
avoid software engineering principles as beaurocratic and obfuscatory
(Imagine trying to read a book in which the meaning if every word and
phrase is located somewhere else - highly beaurocratic and not helpfull
(please - this is not meant to start a discussion over the merits of SE)).

What I'm after is links or references to alternate vhdl styles, that
display a certain internal consistemcy of style that has particular
power in certain contexts and benefits from a consistency of style (and
thus readibility and also templateability) in all other contexts.

I vauguely remember M. Treseler used to try to evangelise a particular
syle but can't find that any more. That sort of thing.

I'm into a change of VHDL lifestyle in my VHDL midlife crisis.

Thanks