VHDL -- Some sort of array of std_logic_vectors ?

So for school I need to make a 2-way set associative cache with a
write-back policy and LRU replacement policy.

it's an 8 lines per way and each way is 8 16-bit words.

Thus, I need 9 bits of tag data, etc.

My question is, well, let's take the tag data for example.

I don't want to have 16 9-bit registers to hold the tag data. Such a
design would be a mess to manage when I make the control unit.

Instead, I would like to have 2 boxes each holding 8 9-bit values which
can be written into and read out of via selecting the right set.

The trouble is, I go to such a good engineering school (top 5), they
seem to believe that they don't actually need to teach VHDL or the
design tools. Nah, we can figure those out on our own.

I liken this to teaching the concept of Red-Black trees and then having
them say, "go write a program that implements them!" without them
having actually taught basic structures in code (not to mention a
programming language)...

Anyway, any help would be appreciated. I *think* what I'm asking about
is pretty basic. But I haven't a clue!

Thanks!