VHDL some confusion about states and updating signals

[Adil Sadik]

Hello, I am a bit confused about something and would appreciate to get some help from here.

I have something like that:

In state1 => rx_status <= Dout;

------

In state4 => rx_len <= Dout;

-----

So, in state4 when Dout is being assigned to rx_status what will happen to rx_status ? Will it be changed to ?

Dout is a output port and rx_status and rx_len are temporary signals. I want to use the value of rx_status which is received in state1. So, after state4 will the rx_status will be changed as in sate4 doug is being assigned to rx_len or it will hold the value which was assigned in state1?

Thanks in advance.

 

[KJ]

On Monday, April 9, 2012 12:42:08 AM UTC-4, Adil Sadik wrote:

Hello, I am a bit confused about something and would appreciate to get some help from here.

I have something like that:

In state1 => rx_status <= Dout;

------

In state4 => rx_len <= Dout;

-----

So, in state4 when Dout is being assigned to rx_status what will happen to rx_status ? Will it be changed to ?

Dout is a output port and rx_status and rx_len are temporary signals. I want to use the value of rx_status which is received in state1. So, after state4 will the rx_status will be changed as in sate4 doug is being assigned to rx_len or it will hold the value which was assigned in state1?

Thanks in advance.

Post some real code for a real answer. However, it appears that you intend rx_status to be updated with the value of Dout while in state1 (and no other state); rs_len to be updated with the value of Dout while in state4 (and no other state).

 

[Andy]

On Apr 8, 11:42 pm, Adil Sadik <sadik.a...@gmail.com> wrote:

So, after state4 will the rx_status will be changed as in sate4 doug is being
assigned to rx_len or it will hold the value which was assigned in state1?

No, rx_status retains its last-assigned value, as do all signals and
variables. Be careful about what this implies in HW if you are
synthesizing your code. The ability to remember a previously (WRT
simulation time, not simply execution) assigned value in HW implies a
storage element. In a clocked process that element would be a flip-
flop, perhaps with a clock enable, which is fine. In a combinatorial
process, that storage element would have to be a latch, which is not
generally acceptable in synchronous designs.

Andy