vhdl sm question

[Vadim Rusu]

Hi all,

I have the following SM construct in VHDL. The implementation is on a
APEX20K BGA. My SM gets to checkevnull_state, the EvNull is set, enters
the if cycle, asserts EnableEmptytoRAM but RAMClear never goes high and
the SM is stuck to that state. I have no clue what is going on, any help
will be appreciated.

V.



when checkevnull_state =>
RAMAdvance <= '0';
if (EvNull = '1') then
next_state <= write_null_state;
RAMClear <= '1';
EnableEmptytoRAM <= '1';
else

next_state <= ReadL1A_state;
end if;

when write_null_state =>
SM1Test <= '1';
next_state <= wait_null_state;

when wait_null_state =>
RAMClear<='0';
RAMWrite <= '1';

next_state <= null_state;

 

[ALuPin]

Could you please give more details with regard to the process
in which the state machine is embedded? That is:
Is RAMClear an output signal? Where else in the process is it
set/reset?

when checkevnull_state =
RAMAdvance <= '0';
if (EvNull = '1') then
next_state <= write_null_state;
RAMClear <= '1';
EnableEmptytoRAM <= '1';
else

next_state <= ReadL1A_state;
end if;

when write_null_state =
SM1Test <= '1';
next_state <= wait_null_state;

when wait_null_state =
RAMClear<='0';
RAMWrite <= '1';

next_state <= null_state;

 

[Vadim Rusu]

The state machine has multiple branches which all set RAMClear and yes,
the RAMClear is an output signal that is used to reset the RAM address
counter. However, I know the process gets to the checkevnull_state,
since I see EnableEmptytoRAM going high. At the same time, SM1Test does
not go high, therefore, my conclusion that the state machine is stuck on
the conditional from checkevnull_state.

Thanks,
V.

ALuPin wrote:

Could you please give more details with regard to the process
in which the state machine is embedded? That is:
Is RAMClear an output signal? Where else in the process is it
set/reset?



when checkevnull_state =
RAMAdvance <= '0';
if (EvNull = '1') then
next_state <= write_null_state;
RAMClear <= '1';
EnableEmptytoRAM <= '1';
else

next_state <= ReadL1A_state;
end if;

when write_null_state =
SM1Test <= '1';
next_state <= wait_null_state;

when wait_null_state =
RAMClear<='0';
RAMWrite <= '1';

next_state <= null_state;

 

[ALuPin]

Could you please show the VHDL code of the complete process ?

Rgds