VHDL Simulation delays

Hi everybody,
I am new to VHDL and have just started tackling the VHDL simulation. I
have read that in signal assignments of the type:

a <= b after 10 ns;

the 'after' clause is ignored in synthesis. Ok, but when should I use
such clauses in the simulation? They are very useful in the
testbenches, but when and why should I use such clauses in the VHDL
sources that will be later synthesized? Also, I am using XST from
Xilinx, here is an excerpt from the synthesis report:

Minimum period: 2.546ns (Maximum Frequency: 392.773MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 7.683ns
Maximum combinational path delay: No path found

Can anyone tell me how the frequency is computed? Is this the maximum
frequency that my design is able to operate at? What influences the
maximum frequency?
Also, what is the meaning of "mininum input arrival time"(probably the
time before the clock that an input signal must be stable and valid?),
"maximum output required time after clock"(maybe the time after clock
that an output signal must remain stable and valid?) and "maximum
combinational path delay"(maybe the largest combinational path - but
path between what signals - inputs and outputs defined in the 'ports'
section of the top level entity)?
Thank you in advance!

Best regards,
Stoyan Shopov