VHDL simple question: is 2-D array synthesizable

[Jimmy]

Dear All,
I need to store and process 88 data(each is 8 bits), I use two
dimensional array to define a new data type. My questions are:
1. Is 2-D array synthesizable ?
2. I can't use downto with 2-D array ? such as the followings, which
results in syntax error.
.....
type ChipBuffer is array (0 to 87) of std_logic_vector(7 downto 0);
singal ,ChipBuffer_I2 : ChipBuffer ;
.....
ChipBuffer_I2(87 downto 1) <= ChipBuffer_I1( 86 downto 0);

error: ChipBuffer_I1 can not be used with range downto;

So what can I use to replace the 2-D array in this case ,
Many thanks!

Jimmy

 

[Nicolas Matringe]

Jimmy a écrit:

Dear All,
I need to store and process 88 data(each is 8 bits), I use two
dimensional array to define a new data type. My questions are:
1. Is 2-D array synthesizable ?

Not as such, IIRC.
Note that your array is not a 2-D array but an array of arrays, which is
synthesizable.

2. I can't use downto with 2-D array ? such as the followings, which
results in syntax error.

You can but not as you did (see below)

....
type ChipBuffer is array (0 to 87) of std_logic_vector(7 downto 0);
singal ,ChipBuffer_I2 : ChipBuffer ;
....
ChipBuffer_I2(87 downto 1) <= ChipBuffer_I1( 86 downto 0);

error: ChipBuffer_I1 can not be used with range downto;

You declared ChipBuffer type with ascending range, you must use an
ascending range when using signals of type ChipBuffer:
ChipBuffer_I2(1 to 87) <= ChipBuffer_I1(0 to 86);

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Jimmy]

Thanks a million to Nicolas Matringe !!!, solve the problem according to
your suggestion ,
Jimmy,

"Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message
news:40B1FF2B.3090702@numeri-cable.fr...

Jimmy a écrit:
Dear All,
I need to store and process 88 data(each is 8 bits), I use two
dimensional array to define a new data type. My questions are:
1. Is 2-D array synthesizable ?

Not as such, IIRC.
Note that your array is not a 2-D array but an array of arrays, which is
synthesizable.


2. I can't use downto with 2-D array ? such as the followings, which
results in syntax error.

You can but not as you did (see below)


....
type ChipBuffer is array (0 to 87) of std_logic_vector(7 downto 0);
singal ,ChipBuffer_I2 : ChipBuffer ;
....
ChipBuffer_I2(87 downto 1) <= ChipBuffer_I1( 86 downto 0);

error: ChipBuffer_I1 can not be used with range downto;

You declared ChipBuffer type with ascending range, you must use an
ascending range when using signals of type ChipBuffer:
ChipBuffer_I2(1 to 87) <= ChipBuffer_I1(0 to 86);

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Hendra Gunawan]

I have Verilog and VHDL code which has 2D array. They are synthesized
correctly with Xilinx XST. But it won't compile with Altera MaxPlus II.

Hendra

 

[Austin Lesea]

Hendra,

Max II has no RAM in the logic plane, so it only seems natural that a 2D
array (which looks like RAM) would not be easily recognized.

One should be able to use each LE as a FF in the array, but that is
pretty inefficient, and would chew up all resources pretty fast.

There is user flash memory available, and perhaps the synthesis tools
require special directives to use it.

What Xilinx parts "synthesized correctly?"

Just curious.

Sounds like a FPGA application, not a CPLD application.

Austin

Hendra Gunawan wrote:

I have Verilog and VHDL code which has 2D array. They are synthesized
correctly with Xilinx XST. But it won't compile with Altera MaxPlus II.

Hendra

 

[Hendra Gunawan]

"Austin Lesea" <austin@xilinx.com> wrote in message
news:c90kbj$ljb3@cliff.xsj.xilinx.com...

What Xilinx parts "synthesized correctly?"

I just tried to inferred a RAM with 2D array

reg [7:0]q[7:0]; //two dimensional array.

In the synthesis report, it said "Found 64 bit register" or something like
that!
It worked in the Xilinx FPGA exactly the way I want it, which is an 8x8 RAM.

Hendra

 

[Martin Thompson]

Austin Lesea <austin@xilinx.com> writes:

Hendra,

Max II has no RAM in the logic plane, so it only seems natural that a
2D array (which looks like RAM) would not be easily recognized.

I think the OP is referring to the Max Plus II (which I tend to
abbreviate to MP2) tool, not the MaxII devices. IIRC the MP2 VHDL
compiler can't do 2d arrays (and indeed many other things). Quartus
probably can.

One should be able to use each LE as a FF in the array, but that is
pretty inefficient, and would chew up all resources pretty fast.

Indeed that would happen if the tools recognised the array - if you
instantiate an LPM_RAM this is what will happen in devices without RAM
blocks (like the old Flex 6K)

<snip>

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt