VHDL signal generation on FPGA...Help..

[Alan Fitch]

bobster.thelobster@yahoo.co.nz wrote:

Hi rossalbi

You have missed Count out of your process sensitivity list and you
have RST and CLK in there, is that causing confusion?

Other than that, If its just a test I'd replace this:

process (CLK, RST)
begin
case Count is
when "0000000000000000000000" => LEDs <= "00000001";
when "0000000000000000000001" => LEDs <= "00000010";
when "0000000000000000000010" => LEDs <= "00000100";
when "0000000000000000000011" => LEDs <= "00001000";
when "0000000000000000000100" => LEDs <= "00001001";
.
.
when "0000000000000001111110" => LEDs <= "01000000";
when "0000000000000001111111" => LEDs <= "10000000";
when others => LEDs <= "00000000";
end case;
end process;
with this

LED's <= Count(7 downto 0);
-----------------------------------------------------------------------------------
If you need to be specific I'd do something like this

Process(count, LEDs)

You don't need LEDs in the sensitivity list, only inputs (assuming the
intention is to have a combinational process, i.e. without flip-flops),

Alan
Doulos
http://www.doulos.com

 

[rossalbi]

hi, i have writen a pice of code which should impliment a value on the
LEDs of my FPGA development board as the signal 'count' increases.
However it is going strait to the ' when others => LEDs <= "00000000";
' value.

any help would be much appreciated...




-- Declare signals
signal CLK : std_logic;
signal RST : std_logic;
signal Count : std_logic_vector(21 downto 0);
signal LEDs : std_logic_vector(7 downto 0);
signal LEDVal : std_logic_vector(7 downto 0);
signal Dir : std_logic;

begin

-- Tie unused signals
User_Signals <= "ZZZZZZZZ";
IO_CLK_N <= 'Z';
IO_CLK_P <= 'Z';
IO <= (0=>LEDs(0), 1=>LEDs(3), 41=>LEDs(4), 42=>LEDs(1),
43=>LEDs(4),
44=>LEDs(5), 45=>LEDs(2), 46=>LEDs(7), others => 'Z');

-- Clock divider
process (CLK, RST)
begin
if (RST='1') then
Count <= (others=>'0');
elsif (CLK'event and CLK='1') then
Count <= Count + 1;
end if;
end process;



process (CLK, RST)
begin

case Count is
when "0000000000000000000000" => LEDs <= "00000001";
when "0000000000000000000001" => LEDs <= "00000010";
when "0000000000000000000010" => LEDs <= "00000100";
when "0000000000000000000011" => LEDs <= "00001000";
when "0000000000000000000100" => LEDs <= "00001001";
.
.
when "0000000000000001111110" => LEDs <= "01000000";
when "0000000000000001111111" => LEDs <= "10000000";

when others => LEDs <= "00000000";
end case;



end process;

-- Instantiate interfaces component

 

Hi rossalbi

You have missed Count out of your process sensitivity list and you
have RST and CLK in there, is that causing confusion?

Other than that, If its just a test I'd replace this:

process (CLK, RST)
begin
case Count is
when "0000000000000000000000" => LEDs <= "00000001";
when "0000000000000000000001" => LEDs <= "00000010";
when "0000000000000000000010" => LEDs <= "00000100";
when "0000000000000000000011" => LEDs <= "00001000";
when "0000000000000000000100" => LEDs <= "00001001";
.
.
when "0000000000000001111110" => LEDs <= "01000000";
when "0000000000000001111111" => LEDs <= "10000000";
when others => LEDs <= "00000000";
end case;
end process;
with this

LED's <= Count(7 downto 0);
-----------------------------------------------------------------------------------
If you need to be specific I'd do something like this

Process(count, LEDs)

Begin

If count = "00"&x'00000" then
LEDs <=x"00";

Else if count = "00"&x'00001" then
LEDs <=x"01";

elsif count = "00"&x'00002" then
LEDs <=x"02";

elsif count = "00"&x'00003" then
LEDs <=x"03";


elsif count = "00"&x'00004" then
LEDs <=x"04";
......................................
................................. and so on
.........................
Else Null;

End if;
End if;
End process;
Hope that helps Bobster

 

[Thomas Stanka]

On 14 Feb., 22:04, bobster.thelobs...@yahoo.co.nz wrote:

Hi rossalbi

You have missed Count out of your process sensitivity list and you
have RST and CLK in there, is that causing confusion?

No that is just the normal clocked process to infer registers.
The sensitivity is perfect.

bye Thomas

 

[Thomas Stanka]

On 14 Feb., 22:04, bobster.thelobs...@yahoo.co.nz wrote:

You have missed Count out of your process sensitivity list and you
have RST and CLK in there, is that causing confusion?

Having Clk and Rst in the sensitivity list is good practice, to have
the LEDs driven directly from FF.
But you need of course a
if rst = '1' then
elsif rising_edge(clk) then
end if
around the multiplexer for this sensitivity list.
Bobster is right if you don't like to have the LEDs driven from FF.

bye Thomas