VHDL sharing components?

[Matt Johnson]

I'm not sure if this is possible, as I haven't been able to think of a way to do it with my limited knowledge of VHDL.

I'm making a 4-stage processor (fetch, decode, execute, writeback) in VHDL for a class project. Each of the different stages are supposed to be different VHDL files.

I've put my registers as a component in the execute stage. In my writeback stage, I'm supposed to modify register values with the output of my ALU which is in the execute stage. If my registers are a component of the execute stage, is it possible to share that component with the writeback stage to edit the values? I'm not sure how to approach this...

 

[GaborSzakacs]

Matt Johnson wrote:

I'm not sure if this is possible, as I haven't been able to think of a way to do it with my limited knowledge of VHDL.

I'm making a 4-stage processor (fetch, decode, execute, writeback) in VHDL for a class project. Each of the different stages are supposed to be different VHDL files.

I've put my registers as a component in the execute stage. In my writeback stage, I'm supposed to modify register values with the output of my ALU which is in the execute stage. If my registers are a component of the execute stage, is it possible to share that component with the writeback stage to edit the values? I'm not sure how to approach this...

You don't really want to "share a component." What you want is to
provide a port for writing the register file. That is you need to
look at your registers like a RAM that has address, data write enable
pins. If the registers physically exist in one module, then you need
to make these signals ports so they can be accessed by another module.
The registers themselves, and the process to write and read them
are all in one module.

It really helps to start by drawing a simplified block diagram of
your system and figure out what signals you need to pass between
the various modules. Then define what the requirements are for
the signals, for example how the "RAM" gets written - when does
the write data need to be valid with respect to the write enable,
clock, etc.

It's much harder to start writing VHDL right away and trying to
work from a bottom-up approach. Many seasoned veterans of logic
design may prefer to work that way, but it's only possible because
they start with a good idea of the system and its interconnect
requirements.

--
Gabor