VHDL - Replication

[EmbSys]

Hello -

Consider the following:

signal LCD_Data : std_logic_vector( 0 to 31 );
signal data : std_logic_vector( 0 to 7 );

I want to "replicate" data onto LCD_Data, so after assignment:
LCD_Data( 0 to 7 ) is data
LCD_Data( 8 to 15 ) is data
LCD_Data( 16 to 23 ) is data
LCD_Data( 24 to 31 ) is data

I can do this thus:

LCD_Data <= data & data & data & data;

Is there are a better (more elegant?) way?

Thanks

 

[Nicolas Matringe]

EmbSys a écrit:

Hello -

[...]
I can do this thus:

LCD_Data <= data & data & data & data;

Is there are a better (more elegant?) way?

Hi
you can use a for...generate loop:

data_rep : for i in 0 to 3 generate
LCD_data(8*i to 8*i+7) <= data;
end generate;

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[anupam]

All the other logics will consume the same logic and the same hardware will
be generated.
Regards,
Anupam