vhdl range in verilog

[Ivan]

Hi,

how do I use a vhdl range type into a verilog vector?

eg.
vhdl:

type InputRange is
(
line01,
line02,
line03,
....
);

and then in verilog I want to use it like this:

wire [32:0] In_s;
assign In_s[line03] = other_signal;

Is it possible?

thanks
ivan

 

[Mike Treseler]

Ivan wrote:

how do I use a vhdl range type into a verilog vector?
eg.
vhdl:
type InputRange is
(
line01,
line02,
line03,
...
);

Last I used verilog,
enumerations were a do-it-yourself project
something like:

parameter line01 = 1,
line02 = 2,
line03 = 3;

Good luck.

-- Mike Treseler

 

[Jonathan Bromley]

On Fri, 30 Oct 2009 11:42:27 -0700, Mike Treseler wrote:

Last I used verilog,
enumerations were a do-it-yourself project
something like:

parameter line01 = 1,
line02 = 2,
line03 = 3;

Indeed.

SystemVerilog has enums:

typedef enum {nameA, nameB, nameC} namedType;

namedType signal1, signal2;

always @* begin
signal1 = signal2;
if (signal2 == nameB)
...
case (signal1)
nameA: ...;
nameB: ...;
endcase

And so on. Note, though, that these are not truly abstract
enums in the VHDL manner. nameA, nameB, nameC are known to
be 0, 1, 2 respectively. Variables signal1, signal2 use the
underlying type "int" to hold their values. You can even
combine the use of integers and enums:

if (signal1 == 1) // is it nameB?

although you CANNOT copy an integer value into an enum
variable unless you use a type-cast:

signal2 = 0; // syntax error, incompatible types
signal2 = namedType'(0); // same as signal2=nameA

There's even an equivalent for 'image:

$display( signal1.name() );

The underlying data type does not need to be "int".
If you know your opcode or state variable or whatever
has a certain number of bits, you can say so:

typedef reg [1:0] {op0, op1, op2, op3} opcodeType;

And you can express custom encodings explicitly:

typedef reg [2:0] {
stateA = 3'b100,
stateB = 3'b010,
stateC = 3'b001 } onehotStateType;

All this is OK for synthesis, if the alignment of the
planets is favorable and your karma is sufficiently
well balanced.

SystemVerilog enums are not the same as VHDL enumerated
types; they have different strengths and weaknesses.
But they are often useful for the same kinds of things.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Brian Drummond]

On Fri, 30 Oct 2009 23:18:36 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

SystemVerilog has enums:

typedef enum {nameA, nameB, nameC} namedType;

namedType signal1, signal2;
...
case (signal1)
nameA: ...;
nameB: ...;
endcase

And so on. Note, though, that these are not truly abstract
enums in the VHDL manner.

The syntax shown here looks similar to C's version of enumerations.

Does SV follow VHDL, in that you can write code that works,

for i in namedType'range loop
...
end loop;

or is it broken by design like C where you have to write

for(i=nameA;i<=nameC;i++) {
...
}

and your code falls over when you modify the enum?

- Brian

 

[Jonathan Bromley]

On Sat, 31 Oct 2009 11:04:57 +0000, Brian Drummond wrote:

The syntax shown here looks similar to C's version of enumerations.

Indeed so.

Does SV follow VHDL, in that you can write code that works,

for i in namedType'range loop
...
end loop;

or is it broken by design like C where you have to write

for(i=nameA;i<=nameC;i++) {
...
}

and your code falls over when you modify the enum?

A bit of both

SV has a "foreach" loop that is very good at iterating
over arrays, but I haven't yet managed to badger the
committees into extending it to scan over the values
of a discrete type. (That's on my list for a possible
future SV-201x, if it ever happens.) However, you *can*
scan over an enum, with modest difficulty:

typedef enum ....... T;
...
T i;
i = i.first(); // silly, you can't do T.first() :-(
do begin
..... whatever ....
i = i.next();
end while (i != i.first());

The (i != i.first()) idiom works because i.next() wraps
around from i.last() to i.first(). There are several
other possible ways to do it:

i = i.first();
repeat (i.num()) begin
... whatever ...
i = i.next();
end

etc, etc, etc.

Note the need to initialize "i=i.first()", because an
enum variable in SV initializes not to its leftmost
value, but to the usual initialization value of its
underlying integral type - zero for 2-state types,
Xs for 4-state types. This initialization value is
not even guaranteed to be a valid member of the enum's
set of literals!

Please, when reading this, always remember how everyone
dislikes VHDL because of its verbosity..... hmmmm.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.