VHDL question

Guest
Hello folks,

I would like to assign a bit in std_logic_vector array to a std_logic
value, is it permissible? i assume that std_logic_vector IS ARRAY OF
std_logic type !

I have mentioned below few piece of my code for illustration:
(its a part of my testbench)

I need to sent each bit of the std_logic_vector array at every clock
cycle.

--Declarations

D : std_logic;
data_in : std_logic_vector(31 downto
0):="01010000000000000000001100000000"



Data_inp: process(clk)
begin
if (clk'event and clk = '1') then
for i in 0 to data_in'length loop
D <= data_in(i);
end loop;
end if;
end process Data_inp;

ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
(I assume it says that we can assign 32 bits to a one bit std_logic)


Thanks in Advance,
ALI
 
--There was a typo in my previous message

Hello folks,


I would like to assign a bit in std_logic_vector array to a std_logic
value, is it permissible? i assume that std_logic_vector IS ARRAY OF
std_logic type !


I have mentioned below few piece of my code for illustration:
(its a part of my testbench)


I need to sent each bit of the std_logic_vector array at every clock
cycle.


--Declarations


D : std_logic;
data_in : std_logic_vector(31 downto
0):="0101000000000000000000110­0000000"


Data_inp: process(clk)
begin
if (clk'event and clk = '1') then
for i in 0 to data_in'length loop
D <= data_in(i);
end loop;
end if;
end process Data_inp;


ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
(I assume it says that we can't assign 32 bits to a one bit std_logic)


Thanks in Advance,
ALI
 
jahaya@gmail.com a écrit :
Hello folks,

I would like to assign a bit in std_logic_vector array to a std_logic
value, is it permissible? i assume that std_logic_vector IS ARRAY OF
std_logic type !
Sure!
Click to expand...

I have mentioned below few piece of my code for illustration:
(its a part of my testbench)

I need to sent each bit of the std_logic_vector array at every clock
cycle.

--Declarations

D : std_logic;
data_in : std_logic_vector(31 downto
0):="01010000000000000000001100000000"



Data_inp: process(clk)
begin
if (clk'event and clk = '1') then
for i in 0 to data_in'length loop
D <= data_in(i);
end loop;
end if;
end process Data_inp;

ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
(I assume it says that we can assign 32 bits to a one bit std_logic)
Just read *your* code: 0 to data_in'length is 0 to 32. And data_in(32)
Click to expand...
is
not allowed.

You should write: for i in data_in'range loop

BTW, the loop is useless and equivalent to:
D <= data_in (0);

Just read your code and the error messages.

JD.
 
Here you go...
If you ever synthesize this, you should reset the counter variable
(index_cnt) before using it, probably by adding a reset input of some
sort.

--Declarations
D : std_logic;
data_in : std_logic_vector(31 downto
0):="01010000000000000000001100000000"

Data_inp: process(clk)
variable index_cnt : std_logic_vector(4 downto 0) := "00000";
begin
if (clk'event and clk = '1') then
D <= data_in(conv_integer(index_cnt));
index_cnt := unsigned(index_cnt) + 1;
end if;
end process Data_inp;

The thing you were doing with the loop is pointless as you were
multiply assigning values to D, in which case only the last assignment
counts. For loops are different in VHDL than in programming. Also, if u
use numeric_std as opposed to std_logic_arith you need to replace
conv_integer with to_integer. Hope this helps
 
jahaya@gmail.com wrote:
Hello folks,

I would like to assign a bit in std_logic_vector array to a std_logic
value, is it permissible? i assume that std_logic_vector IS ARRAY OF
std_logic type !
Click to expand...
Yes, you can.

I have mentioned below few piece of my code for illustration:
(its a part of my testbench)

I need to sent each bit of the std_logic_vector array at every clock
cycle.

--Declarations

D : std_logic;
data_in : std_logic_vector(31 downto
0):="01010000000000000000001100000000"

Data_inp: process(clk)
begin
if (clk'event and clk = '1') then
for i in 0 to data_in'length loop
D <= data_in(i);
end loop;
end if;
end process Data_inp;

ERROR: FATAL ERROR : Index 32 out of range(31 downto 0).
(I assume it says that we can assign 32 bits to a one bit std_logic)
Click to expand...
I'm not going to give you the answer straight up. You'll have to work
out the details for yourself. Given:

signal data_in : std_logic_vector(31 downto 0);

What is the value of:

data_in'length

?

Once you answer that, the cause of the fatal error should be obvious.

Having said that, your loop still won't do what you want. (Homework:
Why not?)

Perhaps a simpler way of doing what you want would be:

DriveBit : process is
begin
for i in data_in'range loop
D <= data_in(i);
wait until rising_edge(clk);
end loop;
end process DriveBit;

-a
--a
 
Well the FAQ can:
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#concat

Egbert Molenkamp

"Florin Franovici" <ffranovici@redlinecommunications.com> schreef in bericht
news:bilji0$adfr0$1@ID-95060.news.uni-berlin.de...
Hello all,

Can anybody tell me the differences on concatenation operator in VHDL-87
and
VHDL-93?

Thanks
Click to expand...
 
Thanks for your help.

Florin

"Egbert Molenkamp" <molenkam_no_spam@cs.utwente.nl> wrote in message
news:bilm2s$9de$1@ares.cs.utwente.nl...
Well the FAQ can:
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#concat

Egbert Molenkamp

"Florin Franovici" <ffranovici@redlinecommunications.com> schreef in
bericht
news:bilji0$adfr0$1@ID-95060.news.uni-berlin.de...
Hello all,

Can anybody tell me the differences on concatenation operator in VHDL-87
and
VHDL-93?

Thanks
Click to expand...
 
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