VHDL propagation time

[Binary]

Hi,

I am a newbie, and I have a question about VHDL(FPGA) propagation time.
For example, a signal is triggered by another, then there is a
propagation time between these two signals, in Quartus II I find the
time is about 6 ns. I would like to know how this value is determined,
it is decided by the IC chip or other settings?

And I also noticed that we can point a time for signal change such as:

q0 <= 0 after 10ns;

How to implement this 10ns delay and what is the relationship with the
propagation time?

Thanks in advance.

Binary Chen

 

[Ralf Hildebrandt]

Binary wrote:

I am a newbie, and I have a question about VHDL(FPGA) propagation time.
For example, a signal is triggered by another, then there is a
propagation time between these two signals, in Quartus II I find the
time is about 6 ns. I would like to know how this value is determined,
it is decided by the IC chip or other settings?

Somebody has measured it or has developed a model for the propagation
time, that fits close enough to reality.
It depends on the driving strength of the gates and their capacitive load.

And I also noticed that we can point a time for signal change such as:

q0 <= 0 after 10ns;

How to implement this 10ns delay and what is the relationship with the
propagation time?

There is no way, because this statement is not synthesizable.

The common way to "make a delay" is to use a (fast) clock, count it for
a number of times and then do something.

Ralf

 

[Binary]

Hi Ralf,

But I noticed some example use the word 'after' havily, so these
examples all just can be simulated but not synthesizable to actual
chip?

Thanks.

Binary Chen

 

[Jerry Coffin]

Binary wrote:

Hi Ralf,

But I noticed some example use the word 'after' havily, so these
examples all just can be simulated but not synthesizable to actual
chip?

At least with the synthesizers of which I'm aware, an 'after' clause
doesn't prevent synthesis -- the logic part of the statement is
synthesized, and the 'after' part is ignored. For example:

output <= input1 or input2 after 1 ns;
and:
output <= input1 or input2 after 100 ns;

would both synthesize perfectly well -- but they'll produce identical
results: an OR gate, with no extra delay added at all.

As mentioned elsethread, if you want a delay in your circuit, you'll
have to do it yourself, typically by counting clock pulses.

 

Hi,

Binary schrieb:

But I noticed some example use the word 'after' havily, so these
examples all just can be simulated but not synthesizable to actual
chip?

Take it the other way round:
You can't have a signal travelling aorund without any delay in real
chips.
If you use after clause, you could have a bit delay for simulation.
This delay won't hit the actual chip, but give you a feeling.

Another point is that the following code will behave different in
simulation and real HW, this could be fixed by using after clause, when
updating signals inside clocked process.

clk1<=clk2;
p1: process (clk1)
begin
a<=b;
end
p2: process (clk2)
begin
b<=a;
end

Last point is that after clause help you delay output to clk so you
could easier see, if a signal transaction is before or after a rising
edge of clock.

Of course you need to know that after is simulation only, and you need
to know what happens if you use after the wrong way(eg after > clk
periode).

bye Thomas

 

[Binary]

Hi Ralf,

But I noticed some example use the word 'after' havily, so these
examples all just can be simulated but not synthesizable to actual
chip?

Thanks.

Binary Chen