VHDL powerup reset module for Altera FPGA

[lsha]

Hi,
I seem to remember there is a VHDL entity for Xilinx FPGA for powerup
reset. Is there a similar code for Altera?

Right now I am using the following process to reset the Altera Cyclone
chip. But this would generate a huge fanout from nReset, which goes to all
F/Fs.

process(Clk)
begin
if Clk'event and Clk = '1' then
if nReset = '0' then
powerOn <= powerOn + '1';
end if;
nReset <= powerOn(3);
end if;
end process;

I know for FPGA once powerup configuration is done the chip is eccentially
in a known state but since all my clocked process has this structure for
easy simulation reset:

if nReset = '0' then
-- reset
elsif clk'event and clk = '1' then
-- work
end if;

I need something physical in the chip to do the same thing.

Thanks in advance.
lsha