VHDL port mapping

[Pradeep]

I have a user defined memory component

rd_clk, wr_clk, wr_ebl : in std_logic
byte_en : in std_logic_vector [3:0]

wr_data : in std_logic_vector[31:0]
wr_addr : in std_logic_vector[6:0]

rd_addr : in std_logic_vector[7:0]
rd_data : out std_logic_vector[15:0]

--
Note: I did not follow VHDL syntax in the above lines
--

I understood that it is a dual port memory with 1 read port and 1 write
port
with write enable.


1)
Is it correct if I call the memory as
256 words, 32 bits, 2 port 1 read and 1 write with 1 write enable?



2)
I have a pre-defined memory on the structured ASIC with

wr_data_fixed : in std_logic_vector[31:0]
wr_addr_fixed : in std_logic_vector[7:0]

rd_addr_fixed : in std_logic_vector[7:0]
rd_data_fixed : out std_logic_vector[31:0]


--
Note: Compare the bit vector sizes, for the user needed memory and the
for t
he memory available on structured ASIC.
--

Is it possible that I use this available memory on structured ASIC, for
the
user purpose memory? If yes, How should I port map them, with different
bit-
vector sizes?


Thanks,
Pradeep

 

[anupam]

hi,
since the port size in ASIC is larger than the size in the memory ,it
shouldn't be a problem .....
You can use internal signals to port map the two blocks ...

regrds,
Anupam Jain