VHDL-plugin for jedit sidekick?

[Axel Friedrich]

Hello,

anybody has a vhdl-plugin for the sidekick-extension of jedit? (I
would like to use it...) Even a simple "alpha" version would be
appreciated.

Regards,

Axel

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[info_]

Axel Friedrich wrote:

Hello,

anybody has a vhdl-plugin for the sidekick-extension of jedit? (I
would like to use it...) Even a simple "alpha" version would be
appreciated.

Regards,

Axel

Are you looking for a syntax coloring file ?
If so, I have done that for MED, it's on my website
http://alse-fr.com/english
(Tech Corner, Utilities, MED syntax coloring)

Hope this helps,

Bert Cuzeau

 

[Axel Friedrich]

Are you looking for a syntax coloring file ?
If so, I have done that for MED, it's on my website
http://alse-fr.com/english
[...]

Hello Bert,


thank You for Your answer and Your offer. But I do not mean syntax
highlighting. What I'm looking for is sometimes called "structure
browser" or in other programming languages "class browser". It is a
window with a list of all classes (for VHDL it could show all
process-names, if given, procedure names, function names, ...) and
when clicking a certain name the editor jumps to this part of the
sourcecode.

The editor "jedit" has a plugin named "sidekick", which could provide
this, but sidekick neads another extension for evaluating the
structure (processes, functions, procedures, ...) of the VHDL code.
This extension can be a selfwriten one... .

BTW, I am very new to vhdl... .


Have a nice weekend,

Axel

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Email see: http://cafriedrich.netfirms.com/email.htm

 

[Mike Treseler]

Axel Friedrich wrote:

thank You for Your answer and Your offer. But I do not mean syntax
highlighting. What I'm looking for is sometimes called "structure
browser" or in other programming languages "class browser". It is a
window with a list of all classes (for VHDL it could show all
process-names, if given, procedure names, function names, ...) and
when clicking a certain name the editor jumps to this part of the
sourcecode.

Emacs has such a "plug-in" called vhdl-mode with a "browser"
called speedbar. It covers your list does except for processes.
http://opensource.ethz.ch/emacs/vhdl-mode.html

The modelsim SE GUI has a both text-view
and schematic-view process browsers.
http://www.xilinx.com/publications/xcellonline/partners/xc_modsim44.htm

The editor "jedit" has a plugin named "sidekick", which could provide
this, but sidekick neads another extension for evaluating the
structure (processes, functions, procedures, ...) of the VHDL code.
This extension can be a selfwriten one... .

There are lots of editors with class browsers for
C++, Java, etc and hooks for other languages.
I know of only one instance of someone actually
hooking an editor up for VHDL and that is
Reto Zimmermann's vhdl-mode for emacs.

-- Mike Treseler

 

[info_]

Hi Axel,

yes, Emacs is certainly the way to go for you.

Axel Friedrich wrote:

BTW, I am very new to vhdl... .

You may discover that the features you're looking for might not

be as "necessary" as they may be for C++, due to the nature and
purpose of VHDL (structural descriptions of hierarchical blocks
of limited size not sharing common variable -at least in RTL style-).
That's just my experience.

But Emacs is still full of very nice features, Thanks Reto !

Bert

Have a nice weekend,

You too

 

[Axel Friedrich]

Hello Bert, hello Mike,

The modelsim SE GUI has a both text-view
and schematic-view process browsers.
http://www.xilinx.com/publications/xcellonline/partners/xc_modsim44.
htm

Hmm, I'm using the Modelsim-Version of Altera/Quartus, did not find a
process browser in the text-view, but will look for it again tomorrow
..

Emacs - I always hesitated to use (and to learn to use) it... , but
often read "Emacs can!"

You may discover that the features you're looking for might not
be as "necessary" as they may be for C++,...

I think, that is an important point for me. So I'll look, if the
Modelsim-Version of Altera/Quartus includes a process browser and is
suited for me, because that I can do very easily. If not, I'll going
on using and learning VHDL for another one or two weeks, and if I
still want to have a ...-browser, I'll give me a hit and spend a few
hours trying Emacs.

Thanks for all the kind tips!

Axel

--
Email see: http://cafriedrich.netfirms.com/email.htm

 

[Mike Treseler]

Axel Friedrich wrote:

Hmm, I'm using the Modelsim-Version of Altera/Quartus, did not find a
process browser in the text-view, but will look for it again tomorrow

It's under View, Process.
The schematic verision is View, Dataflow,
but Altera/Quartus does not have this enabled.

Emacs - I always hesitated to use (and to learn to use) it... , but
often read "Emacs can!"

It takes some time to learn,
but the price/performance is large.
Good luck.

-- Mike Treseler

 

[Mike Treseler]

Mike Treseler wrote:

It takes some time to learn,
but the price/performance is large.

Hmm. Guess that would be *small*.
I'd better stay out of marketing.

-- Mike Treseler

 

[Axel Friedrich]

Hello Mike,

It's under View, Process.
The schematic verision is View, Dataflow,
but Altera/Quartus does not have this enabled.

OK, so I know, I need not longer look for it... .

It takes some time to learn,
but the price/performance is large.

I got curious, will see, if there will be some time for trying it.


Thank You all

Axel

 

[Axel Friedrich]

Hello,


1.) "Structure-Browser"
=======================

I found a way to get a "structure-browser" (showing a list of
processes, procedures, functions,...) for VHDL in jEdit; in case,
someone else is interested in, this is how You can get it:


- Download and install the plugin "CodeBrowser"

- As described in the help of "CodeBrowser", download and install
"ctags" from http://ctags.sourceforge.net

- In jEdit: Plugins > Plugin Options... > "CodeBrowser"
Under "ctags Path" type in the entire pathname of the ctags-exe (if
not already done).

- Create a file with the following content:



--langdef=vhdl
--langmap=vhdl:.vhd.vhdl
--regex-vhdl=/^([ \t]*|.*:[
\t]*)((process|procedure|function|entity|architecture|component|([^:]
*PORT[ \t]MAP)|configuration|package)\b(.*))/\1 \2/All/i
--regex-vhdl=/^([ \t]*|.*:[ \t]*)\b(process\b[^-]*)(--)*[
\t]*(.*)/\1 -- \4/Processes/i
--regex-vhdl=/^[ \t]*(begin)[ \t]+--[ \t]ARCHITECTURE/BEGIN
ARCHITECTURE/Processes/i



Important: There must be an empty line at the end of the file!

Save this file as:

for Windows:
...\jedit\ctags.cnf

for Unix/Linux (I did not try):
CodeBrowser's help says: "On unix-like systems that could be
~/.ctags"


- The regular expressions for the ctags-file are by far not perfect.
If You think, You did build a better one, please post it here or to
my email - thanks!


The above worked fine for me, but: *No warranty!*

-------------------------------------------------------------------

2.) Compiling from within jEdit
===============================

BTW, if you want to compile a VHDL-file with MODELSIM from within
jEdit by just pressing for example "F5", you can try:


Edit the file "...\macros\Misc\Run_Script.bsh" as follows:



Behind: path = buffer.getPath() + " ";
Add: bufferDir = dirname( buffer.getPath() );


Behind: else if(mode.equals("vbscript")) {
execScript("Windows Script Host", "wscript " + path);
}
Add: else if(mode.equals("vhdl")) {
execScript("vcom", "vcom -reportprogress 300 -work " +
bufferDir + "\\work " + path);
}



In jEdit: Utilities > Global Options > Edit Shortcuts: "Macros"

Command: "Run Script" > Click into the field "Alternative
Shortcuts" > Press the F5-Button > OK > OK

Optional, but very handy: Install the Plugin "ErrorList" and the
Plugin "Console".

If You choose to do so:
jEdit > Plugins > Plugins Options... > Console > Error
Patterns > VHDL >


Name: VHDL
(probably already in)
Regexp: (.+):..+\\([^\\]+)\.vhd\ *\((\d+)\).+) (has
been wrong)
Warning regexp: leave empty
Extra lines regexp: leave empty
Filename: $f
Line number: $3
Error message: $4

OK > OK

When now pressing "F5" on an open VHDL-file, it will be compiled into
"work"; Errors are shown by the ErrorList-Plugin, and when clicking
on those errors, jEdit jumps to the relevant line in the sourcecode.


Regards,

Axel

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Email see: http://cafriedrich.netfirms.com/email.htm

 

[Axel Friedrich]

Update:

Improved ctags-file:
================


--langdef=vhdl
--langmap=vhdl:.vhd.vhdl
--regex-vhdl=/^([ \t]*(.*):[ \t]*)(process\b(.*))/- P'SS \2/All/i
--regex-vhdl=/^([ \t]*|.*:[ \t]*|[
\t]*pure[\t]*)((pr)ocedu(re)|(fu)(nc)tion|(en)(tity))\b([^\(]*)/\1
\3\5\7\4\6\8\9 /All/i
--regex-vhdl=/^([
\t]*|.*:[\t]*)((archi)tecture|(comp)onent|(config)uration|(package))\
b(.*)/\1\3\4\5\6 \7 \3/All/i
--regex-vhdl=/^[ \t]*.*((lib)rary|(--&lt)[ \t]*(.*)/\2\3 \4/All/i
--regex-vhdl=/^.*[^:]*)PORT[ \t]+MAP\b(.*)/P'MAP \1/All/i


There must be an empty line at the very end!


Folding
=======


1.) Install plugin "Configurable Folding"


2.) Plugins > Plugin Options > Configurable Folding > Edit mode:
vhdl >
Check "Use regular expressions"; uncheck "Use default fold strings"
Fold start string:
(?i)^(\s*|.*:\s*)(process|procedure|function|entity|component|configu
ration)\b.*$

Fold end string:
(?i)^\s*end\s+(process|procedure|function|entity|component|configurat
ion)\b.*|(.*}}}.*)$

OK


(It's good, but not perfect; if You create/get a better one, please
let
me know.)


3.) Utilities > Buffer Options > Editing > Change settings for
mode:
vhdl > Folding mode: custom > OK


Axel