VHDL PLI

S

Sanka Piyaratna

Guest
Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka
 
On Mar 17, 7:19 pm, Sanka Piyaratna <jayasanka.piyara...@gmail.com>
wrote:
Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka
Click to expand...
Look for VHPI standard, recently this was approved by Accellera
committee. VCS, NC and Aldec already supports it, not sure if Modelsim
does (they have their proprietary FLI). We at CVC (www.noveldv.com)
have inhouse expertise in this domain, if needed.

Regards
Ajeetha, CVC
www.noveldv.com
 
"Sanka Piyaratna" <jayasanka.piyaratna@gmail.com> wrote in message
news:12vnu82o4ll4bf0@corp.supernews.com...
Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka
Click to expand...
Hi Sanka,

If you just want to add some C/C++ to your design (and not control the
simulation kernel from your C-code) then I would advice you to look at
SystemC which is probably much easier to use that the VHPI (or Modelsim's
FLI).

Hans
www.ht-lab.com
 
Hi Hans,

Thanks for your reply.

Am I able to develop the testbench in systemC for the RTL in VHDL and
simulate them together?

Sanka

HT-Lab wrote:
"Sanka Piyaratna" <jayasanka.piyaratna@gmail.com> wrote in message
news:12vnu82o4ll4bf0@corp.supernews.com...
Hi,

I was wondering if anyone know about VHDL PLI (Programming Language
Interface).

Cheers,

Sanka

Hi Sanka,

If you just want to add some C/C++ to your design (and not control the
simulation kernel from your C-code) then I would advice you to look at
SystemC which is probably much easier to use that the VHPI (or Modelsim's
FLI).

Hans
www.ht-lab.com
Click to expand...
 
Hi Sanka,

On Mar 18, 3:19 pm, Sanka Piyaratna <jayasanka.piyara...@gmail.com>
wrote:
Hi Hans,

Thanks for your reply.

Am I able to develop the testbench in systemC for the RTL in VHDL and
simulate them together?
Click to expand...
Yes you can. Usually tools give examples of how to do this. I have
done it with VCS-MX, let me know if you need help on that.


Regards
Ajeetha, CVC
www.noveldv.com
 
Great, Thanks Ajeetha.

Sanka

Ajeetha (www.noveldv.com) wrote:
Hi Sanka,

On Mar 18, 3:19 pm, Sanka Piyaratna <jayasanka.piyara...@gmail.com
wrote:
Hi Hans,

Thanks for your reply.

Am I able to develop the testbench in systemC for the RTL in VHDL and
simulate them together?

Yes you can. Usually tools give examples of how to do this. I have
done it with VCS-MX, let me know if you need help on that.


Regards
Ajeetha, CVC
www.noveldv.com
Click to expand...
 
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